Low-voltage CMOS analog circuits

Hosticka, B.J.; Brockherde, W.; Hammerschmidt, Dirk; Kokozinski, Rainer

doi:10.1109/81.477197

Cited by 21 publications

(6 citation statements)

References 18 publications

(3 reference statements)

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“…Since T ox is linearly dependent on Technology (see (1) and Fig. 2) and since V sig depends on the Technology as shown in Fig.…”

Section: Matching Dominated Capacitancementioning

confidence: 97%

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The Effect of Technology Scaling on Power Dissipation in Analog Circuits

Bult¹

2006

Analog Circuit Design

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A general approach for Power Dissipation estimates in Analog circuits as a function of Technology scaling is introduced. It is shown that as technology progresses to smaller dimensions and lower supply voltages, matching dominated circuits are expected to see a reduction in power dissipation whereas noise dominated circuits will see an increase. These finds are applied to ADC architectures like Flash and Pipeline ADC's and it is shown why Pipeline ADC's survive better on a high, thick-oxide supply voltage whereas Flash ADC's benefit from the technology's thinner oxides. As a result of these calculations an adaptation to the most popular Figure-of-Merit (FOM) for ADC's is proposed.

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“…Since T ox is linearly dependent on Technology (see (1) and Fig. 2) and since V sig depends on the Technology as shown in Fig.…”

Section: Matching Dominated Capacitancementioning

confidence: 97%

“…We will assume that the Oxide Thickness scales proportional to the technology's minimum feature size, expressed as L min [15]: (1) with (see Fig.2). For the supply voltage we assume that, below a minimum feature size of 0.7 [um], it scales proportional to the technology, i.e.…”

Section: Calculation Procedures and Assumptionsmentioning

confidence: 99%

The Effect of Technology Scaling on Power Dissipation in Analog Circuits

Bult¹

2006

Analog Circuit Design

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“…Low-voltage circuit techniques for different applications have been compared and analyzed, e.g. for filters in [24], for analog and digital video signal processing [25], and for various applications from sensor readout circuits to RF circuits in [26].…”

Section: Chapter 2 Low Voltage Issuesmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…Over the last decade, the design of analog circuits operating with low supply voltages (1.5 V or less) has become a mandatory target in most digital and analog CMOS integrated circuits [1], [2]. Unfortunately, in mixed-signal environments, the trend towards lowering the power supply of digital circuitries often sacrifices their analog counterparts in terms of speed, noise requirements and linearity.…”

Section: Introductionmentioning

confidence: 99%

Low-voltage linear voltage regulator suitable for memories

Aloisi

Bille

Palumbo

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffers from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 µm standard CMOS technology. The regulator can work with a no-regulated input voltage in the range from 1.3 V to 3 V providing a regulated voltage of 1 V with a load capacitance of 2.2 nF

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Low-voltage CMOS analog circuits

Cited by 21 publications

References 18 publications

The Effect of Technology Scaling on Power Dissipation in Analog Circuits

The Effect of Technology Scaling on Power Dissipation in Analog Circuits

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Low-voltage linear voltage regulator suitable for memories

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