Low V&lt;inf&gt;T&lt;/inf&gt; CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

Kubicek, S.; Schram, T.; Paraschiv, Vasile; Vos, Rita; Demand, M.; Adelmann, Christoph; Witters, T.; Nyns, L.; Ragnarsson, L.-Å.; Hónɡ, Yú; Veloso, A.; Singanamalla, R.; Kauerauf, T.; Röhr, E.; Brus, S.; Vrancken, C.; Chang, V.S.; Mitsuhashi, R.; Akheyar, A.; Cho, H.-J.; Hooker, J.C.; O’Sullivan, Barry; Chiarella, T.; Kerner, C.; Delabie, Annelies; Elshocht, Sven Van; Meyer, K. De; Gendt, Stefan De; Absil, P.; Hoffmann, T.; Biesemans, S.

doi:10.1109/iedm.2007.4418860

Cited by 20 publications

(20 citation statements)

References 2 publications

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“…For high performance and low power applications, band edge workfunction metal gate electrodes for both nMOS and pMOS devices is needed for achieving low V T . Low-V T HK/MG CMOS has been successfully demonstrated with both "gate-last" [43] and "gatefirst" [44,45] integration schemes.…”

Section: New-generation High K and Metal Gate Transistor Technology Fmentioning

confidence: 96%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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Section: New-generation High K and Metal Gate Transistor Technology Fmentioning

confidence: 96%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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“…To achieve this objective millisecond anneal (MSA) has been shown to be a promising technique for the 32 nm node and below [1,2]. On the other hand, Negative Bias Temperature Instability (NBTI), which is characterized by a progressive shift of the transistor threshold voltage (V th ) when high gate voltage is applied, is one of the main aging mechanisms in CMOS devices [3,4].…”

Section: Introductionmentioning

confidence: 99%

Negative Bias Temperature Instabilities induced in devices with millisecond anneal for ultra-shallow junctions

Moras

Martín-Martínez

Rodrı́guez

et al. 2014

Solid-State Electronics

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a b s t r a c tIn this paper the NBTI degradation has been studied in pMOS transistors with ultra-thin high-k dielectric subjected to a millisecond anneal for ultra-shallow junction implantation using different laser powers. An ultrafast characterization technique has been developed with the aim of acquiring the threshold voltage (V th ) shift in relaxation times as short as possible once the electrical stress is removed. It has been observed that increasing the millisecond anneal temperature reduce the NBTI degradation. These results have been explained in the context of the emission and capture probability maps of the defects.

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“…A single metal gate, however, requires tuning the EWF value to obtain the proper n-and p-type threshold voltage. These tuning efforts have given rise to an extensive study of the impact of capping layer, a thin metal oxide incorporated between the Hf-based high-k dielectrics and metal gates, whereby a single metal gate CMOS process can be implemented with either single or dual cap layer approaches [47]- [52]. Thin cap layers (≤ 1 nm) such as Dy 2 O 3 and Al 2 O 3 deposited on the high-k gate dielectric followed by thermal annealing drives the metal atoms of the cap layer into the high-k layer (and bottom SiO x interface layer).…”

Section: Dielectric Capping For Work Function Tuningmentioning

confidence: 99%

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

Tseng¹

2010

Solid State Circuits Technologies

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Introduction Motivation for implementing high dielectric constant gate dielectric for advanced CMOS scalingSemiconductor devices need to have good performance, with a low cost and low power dissipation. For decades, research and development of semiconductor processing technology and device integration have focused on enhancing performance and reducing costs using SiO 2 as the gate dielectric and doped polysilicon as the gate electrode. The most effective way to enhance performance and reduce costs is to scale the device gate length and gate oxide. Scaling the gate length results in fabricating more devices per wafer (i.e., increase the device density) and thus reduce the cost per chip, while scaling the gate oxide enhances the drive current and reduces the short channel effects due to gate length scaling. However, as the gate oxide becomes thinner, the power to operate transistors increases because of greater gate oxide leakage current. To resolve this high gate oxide leakage problem, the mechanism of the carriers tunneling through the gate dielectric must be better understood. In an ideal metal-insulator-semiconductor (MIS) device, the current conduction in the insulator should be zero. In a real MIS device, however, current can flow through the insulating film by various conduction mechanisms. The two primary conduction mechanisms for electron tunneling through high quality gate dielectric are discussed below. Direct tunnelingIn a metal-insulator-semiconductor (MIS) stack, when the oxide voltage (V ox ) is smaller than the metal-insulator barrier height, the electron tunnels directly from the metal electrode into other semiconductor electrode through the insulator. This is known as the direct tunneling process. The equation for direct tunneling current density (current normalized by device area) is proportional to

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Low V<inf>T</inf> CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

Cited by 20 publications

References 2 publications

Challenges of 22 nm and beyond CMOS technology

Challenges of 22 nm and beyond CMOS technology

Negative Bias Temperature Instabilities induced in devices with millisecond anneal for ultra-shallow junctions

The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies

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