Low Transistor Count Storage Elements and their Performance Comparison

Shah, Owais Ahmad; Khan, Imran Ahmed; Nijhawan, Geeta; Garg, Isha

doi:10.1109/icacccn.2018.8748364

Cited by 4 publications

(1 citation statement)

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“…Therefore, it can be said that the power consumption of the circuit is directly related to the architecture of the flip-flops used in the circuit. As a result, it's crucial to cut down on the circuit's overall power usage by designing ultra-low power flip-flops [2].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of High Performance Frequency Divider in 32 nm CMOS Technology for Biomedical Applications

Grewal

Shah

2023

Int. J. Onl. Eng.

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In this paper, a 3-bit frequency divider (FD) using a novel sense amplifier based flip-flop (SAFF) is presented and demonstrated. The delay in this design was meticulously improved resulting in better values of power delay product (PDP).The latching stage of the proposed design makes use of a novel single ended structure. Comparative analysis in 32 nm CMOS technology using T-SPICE revealed significant and quantitative differences between the proposed design and the existing designs. The PDP results were obtained for ±10% voltage variation, wide temperature range of -40 ℃ to 125 ℃ and at extreme corner cases. Results indicated that the PDP of the new design at nominal operating conditions decreased by minimum of 27.28% and maximum of 57.49%. The proposed design was also at par with available design in terms of area and power. The analysis on the FD proved the assertions that the proposed design is a feasible alternative for high performance applications.

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Section: Introductionmentioning

confidence: 99%