Low threading dislocation Ge on Si by combining deposition and etching

Yamamoto, Yuji; Kozlowski, Grzegorz; Zaumseil, P.; Tillack, Bernd

doi:10.1016/j.tsf.2011.10.095

Cited by 45 publications

(44 citation statements)

References 17 publications

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“…1 Therefore the creation of Ge on Si with low defect density is of great interest. Several techniques to grow high quality Ge on Si are reported e. g. in combination with thermal cycling, 2,3 cyclic annealing and etching, 4,5 aspect ratio trapping 6 and nano hetero epitaxy. 7 On the other hand, for optoelectronic devices, Ge-on-insulator (GeOI) substrate is widely used.…”

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confidence: 99%

Selective Lateral Germanium Growth for Local GeOI Fabrication

Yamamoto¹,

Schubert²,

Reich³

et al. 2014

ECS J. Solid State Sci. Technol.

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High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. By plan view TEM, it is shown that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] and [1–10] direction resulting Ge grown toward [010] direction contains no dislocations. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. A root mean square of roughness of ∼0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.

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confidence: 99%

Selective Lateral Germanium Growth for Local GeOI Fabrication

Yamamoto¹,

Schubert²,

Reich³

et al. 2014

ECS J. Solid State Sci. Technol.

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“…Combining the growth of thick Ge layers with subsequent HCl etching, makes it possible to take advantage of the low TDD of thick Ge layers and to create the desired film thickness by etching. Figure 5 shows the Ge thickness dependence (500 nm, 800 nm, and 1300 nm) of TDD for different window sizes (9). As shown for Ge growth in Fig.…”

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confidence: 90%

“…In the case of samples targeted to 500 and 800 nm thick Ge, a slightly lower TDD is obtained in smaller windows. This difference is caused by the slightly higher Ge thickness due to micro4loading effects (9). In the case of the sample with 1300 nm thick Ge, the window size dependence of TDD is not clearly observed, because the thickness dependence of TDD at higher Ge thickness region is smaller compared to lower thickness region.…”

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confidence: 91%

“…Si diffusion occurs near the interface and the deposited Ge layer is slightly tensile strained due to different thermal expansion coefficient of Si and Ge. Figure 4 shows the TDD as a function of Ge thickness (9). In the case of Ge growth with cyclic annealing (○), the TDD is decreasing with increasing Ge thickness and a value of about 7×10 5 cm 42 is achieved for 4.7 µm thick Ge (8).…”

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(Invited) Advanced Germanium Epitaxy for Photonics Application

et al. 2015

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ECSTransactions, 67 (1) 123-134 (2015) 123 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 139.80.123.38 Downloaded on 2015-07-14 to IP ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 139.80.123.38 Downloaded on 2015-07-14 to IP ECS Transactions, 67 (1) 123-134 (2015) 132 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 139.80.123.38 Downloaded on 2015-07-14 to IP

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“…(2) We also take benefit from a special procedure [7]. It consists of depositing first a relative thick Ge layer with low defect density and then to etch back this layer to a lower thickness compatible with the BiCMOS contact scheme.…”

Section: Diode Fabricationmentioning

confidence: 99%