Low threading dislocation density Ge deposited on Si (100) using RPCVD

Yamamoto, Yuji; Zaumseil, P.; Arguirov, T.; Kittler, M.; Tillack, Bernd

doi:10.1016/j.sse.2011.01.032

Cited by 133 publications

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“…However, the 4.2% lattice mismatch between Si and Ge precludes the direct epitaxial growth of high-quality relaxed Ge layers on top of Si wafers. Efforts to overcome this difficulty are still ongoing in Ge-related research [45][46][47][48]. In our study, high-quality Ge channels were successfully grown on top of Si (001) substrates using a two-temperature method.…”

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confidence: 99%

“…The structure consisted of a 1-μm-thick undoped Ge epilayer and a 50 nm heavily n-type doped Ge epilayer with a phosphorous doping concentration of ∼1.0 × 10 19 cm −3 and a degree of relaxation of 104%, calculated from the analysis of measured high-resolution x-ray diffraction symmetrical and asymmetrical reciprocal space maps. This overrelaxation of the Ge channel is attributed to the difference in the thermal expansion coefficients between Ge and Si; i.e., the Ge channel is 100% relaxed during the temperature growth, but is under slight tensile strain after cooling down to RT [46,47,49,50]. The Ge epilayers were measured to have a root mean square roughness below 1 nm by atomic force microscopy (AFM) and had a threading dislocation density of ∼5 × 10 6 cm −2 .…”

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confidence: 99%

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Experimental Demonstration of Room-Temperature Spin Transport inn-Type Germanium Epilayers

et al. 2015

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confidence: 99%

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Experimental Demonstration of Room-Temperature Spin Transport inn-Type Germanium Epilayers

et al. 2015

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“…However, the 4.2% lattice mismatch between Si and Ge precludes the direct epitaxial growth of defect free and high-quality relaxed Ge layers on top of Si wafers. Efforts to overcome this difficulty are still ongoing in Ge-related research [50][51][52]. Wellestablished epitaxial growth techniques and popular for research purposes like solid-source molecular beam epitaxy (SS-MBE), ultra-high vacuum chemical vapour deposition (UHV-CVD) and low-energy plasma-enhanced chemical vapour deposition (LEPE-CVD) are used to grow relaxed Ge buffers on Si.…”

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confidence: 99%

Strained germanium for applications in spintronics

Morrison

Myronov

2016

Physica Status Solidi (a)

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Germanium (Ge) is another group-IV semiconductor material, which recently started attracting tremendous attention in spintronics following success of silicon (Si). The crystal inversion symmetry of Si and Ge precludes the spin relaxation of conduction electrons by the Dyakonov-Perel mechanism, resulting in a long spin relaxation time. Since the proposal of the spin FET in 1990 by Datta and Das, semiconductor materials have been studied for their spin-orbit (S-O) interactions, particularly those that can be modified by an applied electric field, such as the Rashba S-O interaction, in order to create devices that utilise spin modulation and control to perform logic operations. Since then new proposals have appeared. Nowadays they include spin transistors with several different operating principles, spin-based diodes, spin-based field programmable gate arrays, dynamic spin-logic circuits, spin-only logic, spin communication and others. In this review, the focus will be made on presenting recent progress in Ge spintronics including the key advances made. The absence of Dresselhaus S-O coupling in Ge enables a longer spin diffusion length when compared to III-V semiconductor materials. Evidence of a strong Rashba S-O interaction in strained Ge quantum wells has begun to emerge. Also, the first experimental demonstration of room-temperature spin transport in Ge has recently been reported.

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“…1 Therefore the creation of Ge on Si with low defect density is of great interest. Several techniques to grow high quality Ge on Si are reported e. g. in combination with thermal cycling, 2,3 cyclic annealing and etching, 4,5 aspect ratio trapping 6 and nano hetero epitaxy. 7 On the other hand, for optoelectronic devices, Ge-on-insulator (GeOI) substrate is widely used.…”

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Selective Lateral Germanium Growth for Local GeOI Fabrication

Yamamoto¹,

Schubert²,

Reich³

et al. 2014

ECS J. Solid State Sci. Technol.

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High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. By plan view TEM, it is shown that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] and [1–10] direction resulting Ge grown toward [010] direction contains no dislocations. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. A root mean square of roughness of ∼0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.

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Low threading dislocation density Ge deposited on Si (100) using RPCVD

Cited by 133 publications

References 13 publications

Experimental Demonstration of Room-Temperature Spin Transport inn-Type Germanium Epilayers

Experimental Demonstration of Room-Temperature Spin Transport inn-Type Germanium Epilayers

Strained germanium for applications in spintronics

Selective Lateral Germanium Growth for Local GeOI Fabrication

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