Low thermal expansion material (LTEM) cleaning and optimization for extreme ultraviolet (EUV) blank deposition

Kadaksham, Arun John; Teki, Ranganath; Godwin, Milton; House, Matt; Goodwin, Frank

doi:10.1117/12.2011718

Cited by 2 publications

(2 citation statements)

References 6 publications

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“…This starts with improving the surface quality of the glass substrates on which the Mo/Si Bragg reflectors are being deposited. Pit and bump type defects of the glass surface need to be small enough that they do not result in printable defects after the Mo/Si deposition [11]. Achieving this will require improvements in existing fine polishing techniques including the introduction of new methods such as Dressed Photon Nano-Polishing (DPNP), [12].…”

Section: Euv Maskmentioning

confidence: 99%

EUV lithography: progress, challenges, and outlook

Wurm¹

2014

SPIE Proceedings

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Extreme Ultraviolet Lithography (EUVL) has been in the making for more than a quarter century. The first EUVL production tools have been delivered over the past year and chip manufacturers and suppliers are maturing the technology in pilot line mode to prepare for high volume manufacturing (HVM). While excellent progress has been made in many technical and business areas to prepare EUVL for HVM introduction, there are still critical technical and business challenges to be addressed before the industry will be able to use EUVL in HVM.

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Section: Euv Maskmentioning

confidence: 99%

EUV lithography: progress, challenges, and outlook

Wurm¹

2014

SPIE Proceedings

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“…LTEM substrates also have additional challenges with regards to post-CMP cleaning when compared to QZ. 16 …”

mentioning

confidence: 97%

Abrasive-Free Polishing for Extreme Ultraviolet Lithography Mask Substrates

Amanapu

Lagudu

John-Kadaksham³

et al. 2013

ECS J. Solid State Sci. Technol.

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In the development of photo-masks for extreme ultraviolet (EUV) lithography, it is a formidable task to achieve the stringent requirements of angstrom-scale surface roughness, sub-30 nm peak-valley flatness and defectivity in single digits. The majority of the defects present on the substrate arise from the polishing/cleaning processes. Here we describe the effectiveness of depositing an amorphous silicon (a-silicon) thin film to cover the existing defects (e.g. pits, scratches, bumps, embedded and adhered particles) on the surface of EUV substrates followed by polishing the a-silicon film using abrasive-free liquids to help meet the EUV substrate requirements of surface roughness and defectivity (ideally zero pits or bumps greater than 1 nm in depth or height). Chemical mechanical planarization (CMP) using an abrasive-free poly (ethyleneimine) solution showed that both the final surface roughness and removal rate are strongly dependent on polishing pressure. We developed a hybrid two-step CMP process consisting of polishing first at 1 psi to remove sufficient material to eliminate the underlying defects, followed by polishing at 0.5 psi to achieve low surface roughness. Under these polishing conditions, CMP of a-silicon films deposited on EUV mask substrates resulted in a root mean square (RMS) surface roughness of ∼0.09 nm.

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Low thermal expansion material (LTEM) cleaning and optimization for extreme ultraviolet (EUV) blank deposition

Cited by 2 publications

References 6 publications

EUV lithography: progress, challenges, and outlook

EUV lithography: progress, challenges, and outlook

Abrasive-Free Polishing for Extreme Ultraviolet Lithography Mask Substrates

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