Low-temperature processing of SiO 2 thin films by HD-PECVD technique for gate dielectric applications

Abstract

We report on the fabrication and characterization of SiO 2 thin films by high-density plasma enhanced chemical vapor deposition (HD-PECVD) technique at a processing temperature lower than 400 ºC for gate dielectric applications in thin film transistor (TFT) devices. An inductively coupled plasma source was used to couple the rf power to the top electrode. The SiO 2 thin films were fabricated on p-Si wafers using nitrogen, nitrous oxide, and silane precursors. The deposition process was optimized in terms of the effects of rf power, gas flow rates, and system pressure on deposition rate, chemical etch rate, optical properties, and electrical characteristics. The effects of the processing variables on the refractive index, Si-O bond formation, and impurity related bonds were analyzed. The electrical properties of the films were evaluated from the I-V and C-V characteristics of the MOS capacitors. The effects of the SiO 2 film thickness on the electrical characteristics of MOS capacitors were also investigated in the range of 30-100 nm. The influence of the low temperature processed gate dielectric on the performance of 500 Å poly-Si TFTs was evaluated in terms of the transfer and gate leakage characteristics. The microstructural and electrical characteristics of the HD-PECVD deposited SiO 2 thin films suggest their suitability for the low temperature integration of TFTs on glass or other low temperature substrates.

CART-based optimization of core and cladding layers in silicon nitride photonic integrated circuits towards propagation and bend loss minimization

“…Concerning the higher losses of the sputtered SiO 2 uppercladding compared to the HD-PECVD uppercladding in the node splitting, this is the case that the sputtered SiO 2 deposition step was not optimized, especially for this layout, which might lead to some slight conformality problems, which are lower in HD-PECVD, which is optimized especially for this property. 17,18 The reason for the fact that for LPCVD Si 3 N 4 , neither cladding is taken as a node for widths of the waveguide greater than 620 nm can be accounted for by the high confinement of the TE-mode at these widths, which, due to the slightly higher refractive index of LPCVD Si 3 N 4 even increases the confinement. 13 The reason the uppercladding dominates at 350 nmwaveguide width over the undercladding might be because of the non-conformality in combination with the interaction of the mode on the interface between the waveguide and SiO 2 , where there are also air gaps.…”

Poly-Si TFT Technology: Advances in Material, Process and Device Technology

“…Figure 7 demonstrates this trade-off. SLA has been developing High-Density-Plasma based gate-insulator technology in support of next generation TFT requirements (12)(13). Based on the development and process optimization at SLA, superior quality dielectric films have been demonstrated, rivaling in quality that of thermal oxide.…”

Nanostructured silicon thin film solar cell

“…The most common technique is using chemical vapor deposition (CVD). Plasma enhanced CVD (PECVD) technique is useful to obtain poly-Si when the hydrogen content is carefully adjusted [9][10][11][12][13][14][15][16]. Furthermore, low pressure CVD (LPCVD) can also be used for the purpose, but it requires high temperature [17][18][19][20][21][22].…”