Low Temperature Process Technologies for the Next Generation High Performance Polycrystalline Silicon Thin-Film Transistors

Abstract

Low temperature process technologies for high performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are discussed based on the investigations of pulsed laser crystallization, plasma treatment of poly-Si films, and SiO 2 /Si interface formation. Although high density (~10 18 cm -3 ) trap states localized at grain boundaries are introduced to the poly-Si films by laser crystallization, they are efficiently decreased to the order of 10 16 cm -3 by following hydrogen plasma treatment. It is also shown that high quality SiO 2 /Si interfaces with the density of interface trap states (D it ) in the order of 10 10 cm -2 eV -1 are achieved using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). By applying these low temperature process technologies to the fabrication process, high performance poly-Si TFTs with high n-channel mobility (µ n ) of 187 cm 2 V -1 s -1 , low threshold voltage (V th ) of 1.97 V and small subthreshold swing (S) of 210 mV/dec. were obtained. These results indicate that the development of low temperature process technologies that can control trap states is the key to the next generation high performance poly-Si TFTs.