Low-Temperature Microwave Annealing for Tunnel Field-Effect Transistor

Abstract

Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length (λ). This letter compares low-temperature (490°C) MWA with high-temperature (1050°C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage (V BTBT ) indicates clearly that TFET annealed by MWA had a lower λ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of 10 8 , a low subthreshold swing, and an almost negligible drain-induced barrier lowering.Index Terms-Tunnel field-effect transistor (TFET), microwave annealing (MWA), screening tunneling length (λ), band-to-band tunneling (BTBT).

Impact of Crystallization Method on Poly-Si Tunnel FETs

“…It is worth noting that, in contrast to typical negative differential resistance (NDR) behavior shown in forward drain-to-source bias region, a negative differential conductance (NDC) behavior is observed for both the SPC and the MILC TFETs. This unusual phenomenon can be attributed to a hot carrier effect located at the source/channel junction [6]. As shown in Fig.…”

“…1 (e). The on/off current ratio is thus improved from 1.86×10 6 to 7.50×10 6 . In addition, the average S.S. of the MILC TFETs is 313 mV/dec, which is much lower than that of the SPC TFETs (515 mV/dec).…”

“…Therefore, the characteristics of TFETs may be significantly influenced by the crystallization method through different poly-Si grain size and different number of grain boundaries. For example, even with superior gate control ability, the S.S. of the FinTFETs with solid-phase crystallized (SPC) poly-Si channel film [6] is still inferior to that of the simple planar TFETs with metal-induced lateral crystallized This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.…”

32-nm Multigate Si-nTFET With Microwave-Annealed Abrupt Junction

“…We show that the MWA not only suppresses dopant diffusion [18]- [20] but also mitigates the adverse effect of lateral straggle of ion implantation. By combining a multiplegate (MG) device structure with excellent gate controllability, 32-nm lateral n-type Si-TFETs have been reported for the first time with promising characteristics, including a high ON ratio of >5 × 10 7 , and minimal short-channel effect using V G = 2 V and V D = 1 V, which are among the best ever reported in [6], [7], [21], and [22].…”

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

“…After gate patterning, PFET and NFET regions were implanted by BF 2 of 1 x 10 15 cm −2 at 10 keV and phosphorous of 1 x 10 15 cm −2 at 10 keV, respectively. A subsequent S/D activation was performed by microwave annealing (MWA) at 3000W for 300 s to suppress dopant diffusion into channel [25]. After the formation of contact holes and metallization processes, FGA (N 2 95% and H 2 5%) at 400 • C for 300 s was executed to eliminate possible defects at material interfaces and ferroelectric grain boundaries.…”