Low Temperature Cu–Cu Bonding Technology in Three-Dimensional Integration: An Extensive Review

Abstract

Arguably, the integrated circuit (IC) industry has received robust scientific and technological attention due to the ultra-small and extremely fast transistors since past four decades that consents to Moore's law. The introduction of new interconnect materials as well as innovative architectures has aided for large-scale miniaturization of devices, but their contributions were limited. Thus, the focus has shifted toward the development of new integration approaches that reduce the interconnect delays which has been achieved successfully by three-dimensional integrated circuit (3D IC). At this juncture, semiconductor industries utilize Cu–Cu bonding as a key technique for 3D IC integration. This review paper focuses on the key role of low temperature Cu–Cu bonding, renaissance of the low temperature bonding, and current research trends to achieve low temperature Cu–Cu bonding for 3D IC and heterogeneous integration applications.

Demonstration of Low-Temperature Fine-Pitch Cu/SiO₂ Hybrid Bonding by Au Passivation

“…In addition, Cu as metal interconnect for hybrid bonding can provide excellent electrical resistance, anti-electromigration, and thermal conductivity. However, oxidization of Cu induces a requirement of strict bonding conditions, such as high bonding temperature and high vacuum environment, which causes the problems of thermal budget, structural reliability, wafer warpage for the bonding structures [10]. Therefore, the method to reduce Cu-Cu bonding temperature is important to improve the feasibility of Cu/dielectric hybrid bonding for the applications in 3D IC, involving high bandwidth memory (HBM), quantum compute, fifth-generation mobile networks (5G) and artificial intelligence (AI) chips.…”

The Effect of an Ag Nanofilm on Low-Temperature Cu/Ag-Ag/Cu Chip Bonding in Air

“…Although semiconductor devices have achieved remarkable performance improvement and miniaturization of integrated circuits according to Moore's law, semiconductor devices have reached a physical limit in miniaturization, and device scaling means it becomes very difficult to improve the degree of integration due to the rapidly increasing number of inputs/outputs. To improve the degree of integration of semiconductor devices, 3D packaging technologies such as wafer stacking and die stacking are becoming increasingly important, especially in recent heterogeneous integration, and many studies on 3D packaging have been conducted that cover high performance, miniaturization, reliability, and low manufacturing cost [1,2]. Si forming and filling, wafer thinning, and the bonding process are required for 3D packaging fabrication, and the most important unit process is currently the Cu bonding process due to the fine pitch structure and high-performance demands.…”

Shearing Characteristics of Cu-Cu Joints Fabricated by Two-Step Process Using Highly <111>-Oriented Nanotwinned Cu

“…Excellent reliability, small size, high functionality, and low-cost of devices are thus required. However, it is incredibly difficult to shrink down the pitch of solder microbumps below 10 µm [1][2][3][4][5][6][7][8], due to bridging and the side wall wetting effect [9][10][11]. Cu-Cu bonding has shown potential in overcoming the limitation of scaling down into the sub-micron scale, and impede the delay problem of RC signal.…”