Low surface roughness and threading dislocation density Ge growth on Si (001)

Choi, Dong‐Hyun; Ge, Yangsi; Harris, James S.; Cagnon, Joël; Stemmer, Susanne

doi:10.1016/j.jcrysgro.2008.07.029

Cited by 82 publications

(54 citation statements)

References 19 publications

(27 reference statements)

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“…This increase may be understood from Eq. (8). The value of the relaxation time hsi decreases with increasing dislocation density as is to be expected, leading to a corresponding decrease in the electrical conductivity as observed in Fig.…”

Section: à2supporting

confidence: 72%

“…6 Although, some/many aspects of the thermal and electrical transport maybe considered to be independent of the exact fabrication process implemented, two important scattering mechanisms which can depend on the exact nature of the quality of the epitaxial growth are interface roughness and dislocation scattering, these two mechanisms are related to some degree. 7,8 roughness scattering on thermal conductivity has been studied previously, 9,10 although little has been done in the context of thermoelectrics directly where it is important to consider both electrical and thermal transport. However, for strain-balanced multiple quantum well superlattices, the formation of a number of threading edge dislocations is inevitable and dislocations are likely to play a dominant role, in determining the feasibility of such structures.…”

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confidence: 99%

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A study of the impact of dislocations on the thermoelectric properties of quantum wells in the Si/SiGe materials system

Watling

Paul

2011

Journal of Applied Physics

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Thermoelectric materials generate electricity from thermal energy using the Seebeck effect to generate a voltage and an electronic current from a temperature difference across the semiconductor. High thermoelectric efficiency ZT requires a semiconductor with high electronic conductivity and low thermal conductivity. Here, we investigate the effect of scattering from threading dislocations of edge character on the thermoelectric performance of individual n and p-channel SiGe multiple quantum well structures. Our detailed physical simulations indicate that while the thermal and electrical conductivities decrease with increasing dislocation scattering/density, the Seebeck coefficient actually increases with increasing threading dislocation density above 10 6 cm À2 at room temperature, due to an increase in the entropy associated with each carrier. The collective result of these individual effects, is that the present Si-based quantum well designs can tolerate scattering by a threading dislocation density up to $10 8 cm À2, well within the capabilities of modern growth techniques, before significant reductions in ZT due to scattering from threading dislocations is observed.

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Section: à2supporting

confidence: 72%

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confidence: 99%

A study of the impact of dislocations on the thermoelectric properties of quantum wells in the Si/SiGe materials system

Watling

Paul

2011

Journal of Applied Physics

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“…8 Another approach is to deposit Ge directly on Si substrate and then introduce annealing step during and/or after the Ge growth to reduce the TDD. [9][10][11][12][13][14][15] However, this approach results in a much higher TDD of >10 7 cm −2 (Refs. [16][17][18] and severe Si/Ge inter-mixing at the in growth interface.…”

Section: 6mentioning

confidence: 99%

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

et al. 2015

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A method to remove the misfit dislocations and reduce the threading dislocations density (TDD) in the germanium (Ge) epilayer growth on a silicon (Si) substrate is presented. The Ge epitaxial film is grown directly on the Si (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) handle wafer to form a germanium-on-insulator (GOI) substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

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“…However, the 4.2% lattice mismatch between Si and Ge precludes the direct epitaxial growth of high-quality relaxed Ge layers on top of Si wafers. Efforts to overcome this difficulty are still ongoing in Ge-related research [45][46][47][48]. In our study, high-quality Ge channels were successfully grown on top of Si (001) substrates using a two-temperature method.…”

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confidence: 99%

Experimental Demonstration of Room-Temperature Spin Transport inn-Type Germanium Epilayers

et al. 2015

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Low surface roughness and threading dislocation density Ge growth on Si (001)

Cited by 82 publications

References 19 publications

A study of the impact of dislocations on the thermoelectric properties of quantum wells in the Si/SiGe materials system

A study of the impact of dislocations on the thermoelectric properties of quantum wells in the Si/SiGe materials system

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

Experimental Demonstration of Room-Temperature Spin Transport inn-Type Germanium Epilayers

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