Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations

Dubois, Emmanuel; Larrieu, Guilhem

doi:10.1016/s0038-1101(02)00033-3

Cited by 46 publications

(18 citation statements)

References 18 publications

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“…Based on the results of R C and R PtSi obtained on test structures, R SB is the dominating factor accounting for 80%-90% of R SD . Theoretical analysis, such as that in [20], and preliminary simulations suggest that the current 15-nm underlap between the S/D and the gate is excessive and that it is possible to optimize this parameter to further decrease R SD by several hundreds of ohm-micrometers. In addition, the drive-in temperature could be optimized to maximize the effectiveness of DS.…”

Section: Device Fabricationmentioning

confidence: 99%

Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation

Gudmundsson

Hellström

Luo

et al. 2009

IEEE Electron Device Lett.

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Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (≤ 700 • C) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (t Si = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 · 10 15 and 5 · 10 15 cm −2 . Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts. Index Terms-Dopant segregation (DS), FinFET, platinum silicide PtSi, Schottky-barrier (SB)-MOSFET, trigate.

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Section: Device Fabricationmentioning

confidence: 99%

Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation

Gudmundsson

Hellström

Luo

et al. 2009

IEEE Electron Device Lett.

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“…Indeed diffusive metals have been introduced to suppress the voiding that occurs in the silicon films when silicon diffuses into the silicide. One way to overcome these technological difficulties could be to design MOS transistors with metallic source and drain either based on Schottky barriers [101] or modified Schottky barrier [102]. In both cases, selective epitaxy can be suppressed as source and drain are made out of metal.…”

Section: Source and Drain Engineeringmentioning

confidence: 99%

Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

Deleonibus

2006

Eur. Phys. J. Appl. Phys.

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Abstract. Since the end of the last millenium, the microelectronics industry has been facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS device structures or if new device architectures are implemented. Innovations in the electronics history have been possible because of the strong association between devices and materials research. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50 nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power consumption are reviewed. The issues in the field of gate stack, channel, substrate, as well as source and drain engineering are addressed. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (Ge, diamond/graphite carbon, HiK, . . . ), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices. For example, the association of C-diamond with HiK, as a combination for new functionalized Buried Insulators, will bring new ways of improving short channel effects and suppress self-heating. Because of the low parasitics required to obtain high performance circuits, alternative devices will hardly compete against logic CMOS. (Fig. 1) has accelerated the scaling of CMOS devices to lower dimensions continuously despite the difficulties that appear in device optimization. PACSHowever, uncertainties about lithography, economics and physical limitations will probably slow down the evolution. For the first time, since the introduction of poly gate in CMOS devices process, showstoppers other than lithography appear to be attracting special attention and could require some breakthrough or evolution if we want to continue scaling at the same rate. Design could also be affected by this evolution.Which are the main showstoppers for CMOS scaling? In this paper, we focus on the possible solutions and guidelines for research in the next years in order to propose solutions to enhance CMOS performance before we need to skip to alternative devices. In other words, how can we offer a second life to CMOS?To that respect, the roadmap distinguishes today three types of products: High Performance (HP) (Fig. 1), Low a e-mail: sdeleonibus@cea.fr Operating Power (LOP) and Low Standby Power (LSTP) devices. In the HP case, a historical fact will happen by the 32 nm node: the contribution of static power dissipation will become higher than the dynamic power contribution to the total power consumption! This main fact could affect the MOSFET saturation current as can be observedArticle published by EDP Sciences and available at

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“…Platinum silicide (PtSi) is one of the most popular materials used for low Schottky barrier height (SBH) * E-mail: laszcz@ite.waw.pl as a source/drain electrode in Schottky p-MOSFETs (metal-oxide-semiconductor field effect transistors) [1][2][3][4][5][6]. However, in order to position Schottky MOSFETs advantageously with respect to conventional MOSFET technology, the SBH in Schottky barrier MOSFETs should not exceed 0.1 eV [7].…”

Section: Introductionmentioning

confidence: 99%

TEM studies of PtSi low Schottky-barrier contacts for source/drain in MOS transistors

Łaszcz¹,

Ratajczak²,

Czerwiński³

et al. 2011

Open Physics

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Abstract:Transmission electron microscopy methods were used to determine the impact of two different implantation processes on the morphology of platinum silicide layers constituting low Schottky barrier contacts intended as the source/drain in MOS transistors. These processes are very promising candidates for the reduction of the Schottky barrier height (SBH) of contacts and are realized by (i) implantation-through-metal (ITM) followed by dopant-segregation induced by silicidation annealing and (ii) implantation-through-silicide (ITS) followed by dopant-segregation due to the post-silicidation annealing. The studies showed that depending on the type and conditions of the process (ITM or ITS with various post-silicidation annealing temperatures) different morphologies of PtSi layers and PtSi/Si interfaces roughnesses are observed. Better quality silicide layers and silicide/silicon interfaces were found for samples after the ITS process with post-silicidation annealing at 500°C than for samples after the ITM process or the ITS process with post-silicidation annealing at temperatures not exceeding 400°C. The observed microstructure of grains and interfaces in these samples, along with the impact of the dopant-segregation, may significantly influence the SBH value. The diffraction patterns and EDXS measurements revealed that regardless of the process type, the formed silicide layer is always PtSi. PACS

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Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations

Cited by 46 publications

References 18 publications

Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation

Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation

Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond

TEM studies of PtSi low Schottky-barrier contacts for source/drain in MOS transistors

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