Low Power VLSI Design for a RFID Passive Tag baseband System Enhanced with an AES Cryptography Engine

Man, A.S.W.; Zhang, E.S.; Lau, V.K.N.; Tsui, Chi-Ying; Luong, Howard C.

doi:10.1109/rfideurasia.2007.4368097

Cited by 30 publications

(12 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Adam [16] has implemented AES encryption scheme in EPC-Gen2 baseband processor, because of the use of AES, a traditional encryption scheme, the baseband area is as large as 0.45mm 2 . Wei [24] and Yin [26] have designed two low-power and low-cost EPC-Gen2 baseband processors without encryption scheme.…”

Section: E Simulation and Implementation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Implementation of a New RFID Authentication Protocol for EPC Gen2 Standard

Liu

et al. 2015

IEEE Sensors J.

View full text Add to dashboard Cite

Researchers have revealed that electronic product code (EPC) Gen2 standard, which is designed for passive ultrahigh-frequency radio frequency identification has various security problems. To solve these problems, some authors have proposed many lightweight protocols to enhance security. However, it is still unclear about the feasibility of such protocols, since the hardware implementation of such protocols has long been neglected. Besides, it is extremely challengeable to achieve the balance among security, low power, and low cost. In this paper, a new lightweight mutual authentication protocol based on variable linear feedback shift registers is proposed, and its security analysis is described. An ASIC implementation of the new protocol compliant with the EPC Gen2 standard is presented as well. Several low-power techniques are used to obtain the goal of low-power consumption. The implementation result shows that the area of the baseband is 0.16 mm 2 and power consumption is 5.5 µW. As far as we know, this is the first ASIC implementation of a lightweight protocol compliant to EPC Gen2 standard. We believe that this design will bring a novel insight to future implementations for EPC Gen2v2 standard, which is ratified recently.

show abstract

Section: E Simulation and Implementation Resultsmentioning

confidence: 99%

“…Adam S. W. Man et al employed AES encryption scheme to achieve a secure transaction for passive UHF RFID at the ASIC level [16]. Due to the adoption of traditional AES cryptographic function, the chip area of tag is very large and the cost is high.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a New RFID Authentication Protocol for EPC Gen2 Standard

Liu

et al. 2015

IEEE Sensors J.

View full text Add to dashboard Cite

show abstract

“…Symmetric cryptography-based protocols using the Advanced Encryption Standard (AES) Rijndael have been proposed for these purposes in a number of publications, e.g. [2] and [8]. Such protocols rely on the existence of low power implementations of the AES that depend on various parameters.…”

Section: Introductionmentioning

confidence: 99%

“…For example, a passive RFID tag baseband system was designed in [8] and consumes 4.7 µW. This is a severe limitation to the power consumption of the AES system.…”

Section: Introductionmentioning

confidence: 99%

Scaling trends of the AES S-box low power consumption in 130 and 65 nm CMOS technology nodes

Kamel

Standaert

Flandre

2009

2009 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

In the recent years, the power consumption of the AES (Advanced Encryption Standard) S-box has been a target for intensive optimization as the power budget of security enhanced RFID (Radio Frequency Identification Devices) tags is limited to a few µW. In this paper, 0.13 µm and 65 nm CMOS technology nodes are thoroughly investigated in order to select the most appropriate one in terms of power consumption and computation delay. Schematic simulation results of full custom S-boxes show that the optimum choice in our context is the LP (Low Power) flavor of the 65 nm node with Standard Vt (SVT) devices. This leads to a power consumption below 100 nW at 100 kHz using nominal 1.2 V supply voltage, which is an order of magnitude lower than what was previously published in the open literature. The reported delay is 2.35 ns. Our study then extends the reduction of the power consumption further by reducing the supply voltage. The power consumption at 100 kHz decreases by 60 % as the supply voltage is reduced to 0.8 V.

show abstract

“…Modeled results for the baseband part of a UHF RFID tag using the AES were reported in [20]. However, the design is rather large (approx.…”

Section: Introductionmentioning

confidence: 99%

A low-frequency RFID to challenge security and privacy concerns

Good

Benaïssa

2009

2009 IEEE 6th International Conference on Mobile Adhoc and Sensor Systems

View full text Add to dashboard Cite

This paper presents a practical realization of a secure passive (battery-less) RFID tag. The tag consists of an off the shelf front end combined with a bespoke O.18JLm ASIC assembled as a credit card sized prototype. The ASIC integrates the authors' ultra low power novel AES design together with a novel random number generator and a novel protocol which provides both security and privacy. The analysis presented shows a security of 64-bits against many attack methods. Both modeled and measured power results are presented. The measured average core power consumed during continuous normal operation is 1.36JLW.

show abstract

Low Power VLSI Design for a RFID Passive Tag baseband System Enhanced with an AES Cryptography Engine

Cited by 30 publications

References 6 publications

Implementation of a New RFID Authentication Protocol for EPC Gen2 Standard

Implementation of a New RFID Authentication Protocol for EPC Gen2 Standard

Scaling trends of the AES S-box low power consumption in 130 and 65 nm CMOS technology nodes

A low-frequency RFID to challenge security and privacy concerns

Contact Info

Product

Resources

About