Low power register file architecture for application specific DSPs

Mueller, M.; Wortmann, Andreas; Simon, Sven; Wolter, S.; Buch, Saket D.; Wróblewski, Marek; Nossek, Josef A.

doi:10.1109/iscas.2002.1010395

Cited by 4 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Various studies have shown that register files are major consumers of energy in modern processors [1][2][3]. Different architectures and techniques have been proposed in the literature [4][5][6][7][8][9] where the primary objective was to optimize the energy consumption of register files. Hence, there exists a justifiable need for the accurate power modeling of these components taking into consideration the current nanometer processing technologies.…”

Section: Introductionmentioning

confidence: 99%

Dynamic and Leakage Power Estimation in Register Files Using Neural Networks

Sagahyroon¹,

Abdalla²

2012

View full text Add to dashboard Cite

Efficient power consumption and energy dissipation in embedded devices and modern processors is becoming increasingly critical due to the limited energy supply available from the current battery technologies. It is vital for chip architects, circuit, and processor designers to evaluate the energy per access, the power consumption and power leakage in register files at an early stage of the design process in order to explore power/performance tradeoffs, and be able to adopt power efficient architectures and layouts. Power models and tools that would allow architects and designers the early prediction of power consumption in register files are vital to the design of energy-efficient systems. This paper presents a Radial Base Function (RBF) Artificial Neural Network (ANN) model for the prediction of energy/access and leakage power in standard cell register files designed using optimized Synopsys Design Ware components and an UMC 130 nm library. The ANN model predictions were compared against experimental results (obtained using detailed simulation) and a nonlinear regression-based model, and it is observed that the ANN model is very accurate and outperformed the nonlinear model in several statistical parameters. Using the trained ANN model, a parametric study was carried out to study the effect of the number of words in the file (D), the number of bit in one word (W) and the total number of Read and Write Ports (P) on the values of energy/access and the leakage power in standard cell register files

show abstract

Section: Introductionmentioning

confidence: 99%

Dynamic and Leakage Power Estimation in Register Files Using Neural Networks

Sagahyroon¹,

Abdalla²

2012

View full text Add to dashboard Cite

show abstract

“…Whenever Filter 2 is executed, the registers of Filter 1 (Dark area in registerfile of Figure 3) should remain ideally unchanged and viceversa. But due to the single registerfile and a common data bus the registers share, any change in the contents of the data bus would cause spurious transitions on the input of all the registers in the register file [7]. These additional transitions results in increased power dissipation.…”

Section: Power Saving Estimationmentioning

confidence: 99%

Power reduction of ASIPs by distributing the workload on several ASIP-instances

Kalyanaraman

Mueller

Simon

et al.

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005.

Self Cite

View full text Add to dashboard Cite

In modern SoC designs, more and more Application Specific Instruction-set Processors (ASIPs) are used. They enable a trade off between the flexibility due to the software implementation of algorithms and hardware efficiency arising from the ASIP architecture which is optimized with respect to the application. In this paper, it is shown that the total power dissipation could be reduced by distributing the software tasks on several identical ASIP instances although the throughput of a single ASIP would be sufficient for all tasks. In addition, it is shown that for power comparisons of processor instances, the number of executed lines of code is a parameter which gives more insight into power comparisons than the clock rate.

show abstract