Low Power Quaternary Adder Using CNFET

Chauhan, Anurag; Mahor, Lokesh; Tiwari, Piyush

doi:10.1109/vlsidcs47293.2020.9179898

Cited by 10 publications

(5 citation statements)

References 9 publications

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“…The state of art CNTFET based quaternary logic gate design has been reported in [38,[43][44][45], and [46]. Also, the state of art CNTFET-based quaternary arithmetic design has been reported in [38,[47][48][49] and [50]. A multiplexer-based quaternary adder, utilizing a sub-10 nm CNTFET technology model file and comprising 287 transistors, was presented in [50].…”

Section: Literature Surveymentioning

confidence: 99%

“…Also, the state of art CNTFET-based quaternary arithmetic design has been reported in [38,[47][48][49] and [50]. A multiplexer-based quaternary adder, utilizing a sub-10 nm CNTFET technology model file and comprising 287 transistors, was presented in [50]. Though the CNTFET-RRAM based implementation of quaternary logic has not been reported in the literature yet, the proposed designs have been compared with the recent CNTFET based quaternary logical and arithmetic circuits.…”

Section: Literature Surveymentioning

confidence: 99%

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Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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Multi-valued logic (MVL), which is an extension of binary logic, is a framework for representing complex systems with more than two truth values. This paper delves into the circuit design, computational aspects, and practical applications of the quaternary logic system, which is a type of MVL with four truth values. The multi-threshold property of carbon nanotube field-effect-transistors (CNTFET), along with resistive random-access memory (RRAM) having the capability of storing multiple resistance values, has been used in the design of quaternary logic gates and arithmetic circuits. The non-volatility in the design achieved using RRAMs enables the circuits to be used in reconfigurable logic and in-memory computational applications. The properties of RRAM, like resistance switching and multi-cell storage, have been used to optimize the proposed circuits. Quaternary logic gates such as inverter, NAND, and NOR, and quaternary arithmetic circuits including decoder, half adder, and multiplier have been designed. The power-delay-product (PDP) of the proposed quaternary inverter, NAND, NOR, half adder, and multiplier is 62.38%, 93.4%, 80.29%, 14.79%, and 20% less than the least PDP of the quaternary designs under consideration, respectively.

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Section: Literature Surveymentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

show abstract

“…Entering the pathway amplifying the FA (t RCA bearing) delay will reduce the RCA prompt. The application of the FA group can be selected to reduce the application delay [17]. 3shows that the carry-in can be computed with g, p, and carry-in [18].…”

Section: (I) Delaymentioning

confidence: 99%

Performance Analysis of High Speed and Low Power Binary Adders

Bhati

Sharma

Nag

2022

IOP Conf. Ser.: Mater. Sci. Eng.

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In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient adding and cumulative operations, so blocks with the required attributes must be carefully selected. Various techniques have been proposed to design efficient adders in terms of performance, low power consumption and area. This work focused on 16-bit implementations of highly optimized area-efficient Ripple Carry Adders (RCA) and Look Ahead Carry Adders (LAC), and carry select Adder. Finally, we can prove that the Carry look ahead Adder is very fast in all existing designs. These processes are simulated and synthesized in all ISE Xilinx 14.7 software.

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“…High power dissipation in these designs is mainly due to its shifting of a large numbers of forged transistors on internal nodes. In array multipliers, the basic building block is the timing analysis of a full adder that has been ensued in a discrete array connection pattern, which decreases power dissipation caused by the transition activity [9].…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2022

Wireless Pers Commun

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Multiplication is one of the basic functions in Digital Signal Processing (DSP) applications. Multiplier plays an important role in Arithmetic and Logic Unit (ALU), which is a critical element in the processors. The e ciency of the multiplier takes part a crucial task in the execution of the processor. The performance of the multiplier depends on the adder circuit. The addition operation is the fundamental operation used in most of the digital circuits. Power, delay and area are the main issues in VLSI circuits. E ciency of a VLSI circuit can be improved by rectifying any of these issues. Quaternary Signed Digits (QSD) placed on adders have better e ciency when compared to traditional binary logic. QSD based Carry Look Ahead (CLA) Adder is used to increase the e ciency with reference to power and delay. The proposed method uses Quaternary Carry Increment Adder in order to improve the power and reduce the delay of the existing Quaternary Carry Look Ahead Adder. Tanner EDA is the simulation tool used to design the circuits and the power, delay and power-delay product of the designed circuits are measured using it.

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Low Power Quaternary Adder Using CNFET

Cited by 10 publications

References 9 publications

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Performance Analysis of High Speed and Low Power Binary Adders

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

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