Low Power Pre-charge Voltage Level and Low Swing Logic Based 8T SRAM Cell for High Speed CMOS Circuits

Rawat, Ram Murti; Kumar, Vinod

doi:10.1109/miel52794.2021.9569198

Cited by 2 publications

(3 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A sequence of leakage current decreases occur when the transistors go from being inactive to being active and vice versa thanks to the precharge voltage level approach, which uses an NMOS transistor as a resister and a PMOS transistor as a switchThe comparison's results demonstrate that the proposed 8T SRAM cell's read, write, and hold mode operation is superior to that of the 6T SRAM cell. This occurs regularly as a result of the increased static noise margins produced, which guarantee good bit cell write ability [5].…”

Section: Introductionmentioning

confidence: 99%

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat

Kumar

2022

Preprint

View full text Add to dashboard Cite

The typical memory for very large scale integrated (VLSI) circuits has traditionally been static random access memory (SRAM). This is so because SRAM is a speedier technology than the ones that were previously mentioned. SRAM, however, has a high power consumption rate. Due to its importance in the memory architecture, it is crucial to lower the power consumption of SRAM cells. This literature review's major goal is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). The static random access memory (SRAM) is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The following is how the paper is divided into sections: 1. Introduction. Section 2 describes related work. The suggested work is in section 3. Results and discussion are included in section 4 and section 5 Conclusions.

show abstract

Section: Introductionmentioning

confidence: 99%

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat

Kumar

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…A sequence of leakage current decreases occurs when the transistors go from being inactive to being active and vice versa thanks to the precharge voltage level approach, which uses an NMOS transistor as a resister and a PMOS transistor as a switchThe comparison's results demonstrate that the proposed 8T SRAM cell's read, write, and hold mode operation is superior to that of the 6T SRAM cell. This occurs regularly as a result of the increased static noise margins produced, which guarantee good bit cell write ability [5].…”

Section: Introductionmentioning

confidence: 99%

“…6. 5 The withdrawal noti cation has now been placed on your preprint, and the title has been hidden from the platform search function. Here is the link to the withdrawn preprint: https://doi.org/10.21203/rs.3.rs-2296617/v1…”

mentioning

confidence: 99%

Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Rawat,

Kumar

2024

Preprint

View full text Add to dashboard Cite

Static random access memory (SRAM) is the typical memory for very large scale integrated (VLSI) circuits. A major reason for this is the high speed operation for SRAM in comparison to its previous counterparts, a major trade off for the circuit is its high power consumption. With the growing importance of memory architectures, it is crucial to lower the power consumption of SRAM cells. This major goal of this paper is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). SRAM is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The paper is organized into the following sections: 1. Introduction, Section 2 describes related work. The suggested work is explained in section 3, while the results and discussion are included in section 4. The results for all the sections are concluded in section 5 conclusions.

show abstract

Low Power Pre-charge Voltage Level and Low Swing Logic Based 8T SRAM Cell for High Speed CMOS Circuits

Cited by 2 publications

References 15 publications

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

WITHDRAWN: Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications

Contact Info

Product

Resources

About