2013 IEEE International Symposium on Consumer Electronics (ISCE) 2013
DOI: 10.1109/isce.2013.6570183
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Low power multi-lane MIPI CSI-2 receiver design and hardware implementations

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Cited by 4 publications
(2 citation statements)
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“…In the case of image sensors (cameras), the most widely adopted serial protocols are those developed by the MIPI alliance [16]. Currently, the Camera Serial Interface (CSI-2) is the de facto standard for these sensors, in both prototyping and consumer electronic devices, due to its good trade-off between high speed and cost effectiveness [17]. CSI-2 is commonly combined with a physical level protocol called D-PHY [18], based on Low Voltage Differential Signaling (LVDS) pairs, with separate physical lanes for data (a maximum of 4) and for a Double Data Rate (DDR), source synchronous clock.…”
Section: Integration With Standard Protocolsmentioning
confidence: 99%
“…In the case of image sensors (cameras), the most widely adopted serial protocols are those developed by the MIPI alliance [16]. Currently, the Camera Serial Interface (CSI-2) is the de facto standard for these sensors, in both prototyping and consumer electronic devices, due to its good trade-off between high speed and cost effectiveness [17]. CSI-2 is commonly combined with a physical level protocol called D-PHY [18], based on Low Voltage Differential Signaling (LVDS) pairs, with separate physical lanes for data (a maximum of 4) and for a Double Data Rate (DDR), source synchronous clock.…”
Section: Integration With Standard Protocolsmentioning
confidence: 99%
“…1 as in the data transmission process diagram, high-speed data transmit in clock triggering.the state state and the end state for data transmission is LP-11, clock enter the high-speed mode after leaving the state of rest through a transmission start state (SOT): LP11-LP01-LP00. clock signal must enter the high-speed mode before triggering of the high-speed data transmission in order to provide the DDR clock with data and must keep the high speed data transmission over to stop the clock signal.the transmission end state (EOT) :LP00-LP11.Similarly, data channel first transmit a start state(SOT) after leaving the state of rest and then transmit a eight bit sequence:00011101, then began to transfer valid bit and enter into the high-speed mode [7]. F.When in high-speed mode transmitting waveform 000111, measuring the rise time of Tr, the measuring range is from 20% to 80% of VOD voltage .…”
Section: Transmission Characteristics Based On D-phymentioning
confidence: 99%