Low-power low-voltage analog electronic circuits using the flipped voltage follower

Ramírez-Angulo, J.; Carvajal, R.G.; Torralba, A.; Galán, J.; Vega-Leal, A.P.; Tombs, J.

doi:10.1109/isie.2002.1025983

Cited by 13 publications

(12 citation statements)

References 6 publications

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“…Applications of FVF include current mirrors [12], [13], differential pair and amplifier [14], [15], low voltage output stages for OP-AMP [14], [16], [17].…”

Section: Flipped Voltage Followermentioning

confidence: 99%

Delay area efficient low voltage FVF based current comparator

Iswerya

Gupta

Goel

et al. 2012

2012 Students Conference on Engineering and Systems

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This paper presents an improved current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit exhibits short propagation delay and occupies a small chip area. The proposed circuit has been simulated employing PSpice simulator for 0.18 µm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.

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“…Applications of FVF include current mirrors [12], [13], differential pair and amplifier [14], [15], low voltage output stages for OP-AMP [14], [16], [17].…”

Section: Flipped Voltage Followermentioning

confidence: 99%

Delay area efficient low voltage FVF based current comparator

Iswerya

Gupta

Goel

et al. 2012

2012 Students Conference on Engineering and Systems

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“…On comparing with conventional voltage followers, the flipped voltage follower (FVF) is more developed and improved voltage follower, therefore it is widely used in various analog integrated circuits these days [2,3]. Some of special features of conventional FVF are [1] that it has almost unity voltage gain on neglecting short-channel effects.…”

Section: Introductionmentioning

confidence: 99%

A new flipped voltage follower with enhanced bandwidth and low output impedance

Gupta

Singh

2012

Analog Integr Circ Sig Process

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The paper proposes a flipped voltage follower (FVF) cell with wider bandwidth and lower output impedance as compared to the conventional FVF. These improvements are obtained by adding a resistance in the feedback path of conventional FVF. A current mirror is implemented by using proposed FVF cell to verify the performance improvement. The circuits are designed in TSMC 0.18-lm CMOS technology with 1.5 V supply voltage. The simulation results show that bandwidth extension ratio (BWER) of newly developed FVF is 1.4 without peaking and 1.7 with peaking. The BWERs of the passive-compensated current mirror implemented by using proposed FVF cell are 1.28 without peaking and 1.58 with peaking in the frequency response.

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“…The development of high-performance integrated voltage regulators, in terms of accuracy, power efficiency, response time, silicon area, and off-chip component free feature, is undoubtedly vital to the success of SoC. To enable these requirements, a low drop out (LDO) with single-transistor control (STC) based on the flipped voltage follower (FVF) [1]- [3], with emphasis on the circuit theory for successful implementation, is presented in this paper [4].…”

mentioning

confidence: 99%

“…A high loop gain, which results in improved steady-state regulation, degrades close-loop stability, so that different methodologies such as an advanced pole-zero can-cellation scheme in [5], a load-dependent reference voltage concept in [6], pole-splitting schemes in [7]- [10], were proposed. Recently, a super source follower [11], in form of FVF [1]- [3], has been applied to the designs of a buffer [12] and a power stage [13] in LDO. The main advantage of the FVF is the reduced output impedance due to shunt feedback connection [11], which is the key for obtaining good regulation and achieving frequency compensation.…”

mentioning

confidence: 99%

“…However, there are, in fact, many design issues have to be studied when using the FVF as a power stage. The studies in [1]- [3] do not focus on LDO design, and the application of the FVF in [12] is not for the power stage. In addition to the impedance control in [13], loop stability is undoubtedly a key issue needed to be analyzed in detail, especially when using different combinations of output capacitor and ESR values [14], [15] or when operating in the no output-capacitor (no-capacitor) condition [7], [8].…”

mentioning

confidence: 99%

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