Low power integrate and fire circuit for data conversion

Rastogi, Manu; Garg, Vaibhav; Harris, John G.

doi:10.1109/iscas.2009.5118351

Cited by 11 publications

(3 citation statements)

References 9 publications

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“…The matrix D is a difference operator which has null space vector c1 N where c ∈ C\{0}. Hence, if there exist a non-zero vector x as in (21) whose components satisfy (9), such that Vx = c1 N for some arbitrary c, then there does not exist a unique solution. We show that for N ≥ 2K + 2 ≥ 2L + 1, uniqueness is guaranteed.…”

Section: Appendixmentioning

confidence: 99%

“…A popular approach for time encoding is an integrate and fire time encoding machine (IF-TEM), which is a braininspired sampling paradigm. It leads to simple and energyefficient devices, such as analog-to-digital converters [9], [11], neuromorphic computers [15], event-based vision sensors [16], [17], and more. In an IF-TEM, a bias is added to the analog input signal to make the signal positive.…”

Section: Introductionmentioning

confidence: 99%

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FRI-TEM: Time Encoding Sampling of Finite-Rate-of-Innovation Signals

Naaman¹,

Mulleti²,

Eldar³

2021

Preprint

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Classical sampling is based on acquiring signal amplitudes at specific points in time, with the minimal sampling rate dictated by the degrees of freedom in the signal. The samplers in this framework are controlled by a global clock that operates at a rate greater than or equal to the minimal sampling rate. At high sampling rates, clocks are power-consuming and prone to electromagnetic interference. An integrate-and-fire time encoding machine (IF-TEM) is an alternative power-efficient sampling mechanism which does not require a global clock. Here, the samples are irregularly spaced threshold-based samples. In this paper, we investigate the problem of sampling finite-rate-ofinnovation (FRI) signals using an IF-TEM. We provide theoretical recovery guarantees for an FRI signal with arbitrary pulse shape and without any constraint on the minimum separation between the pulses. In particular, we show how to design a sampling kernel, IF-TEM, and recovery method such that the FRI signals are perfectly reconstructed. We then propose a modification to the sampling kernel to improve noise robustness. Our results enable designing low-cost and energy-efficient analogto-digital converters for FRI signals.

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Section: Appendixmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

FRI-TEM: Time Encoding Sampling of Finite-Rate-of-Innovation Signals

Naaman¹,

Mulleti²,

Eldar³

2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Many models of neurons have already been implemented in silicon (Mead, 1989;Mahowald & Douglas, 1991;van Schaik, 2001;Hynna & Boahen, 2001;Indiveri, 2003;Alvado et al, 2004;Simoni, Cymbalyuk, Sorensen, Calabrese, & DeWeerth, 2004;Schemmel, Meier, & Mueller, 2004;Arthur & Boahen, 2004Farquhar & Hasler, 2005;Hynna & Boahen, 2006;Wijekoon & Dudek, 2008;Livi & Indiveri, 2009;Yu & Cauwenberghs, 2009;Rastogi, Garg, & Harris, 2009;Massoud & Horiuchi, 2009;Folowosele, Etienne-Cummings, & Hamilton, 2009). Depending on the complexity of the neuron model, the VLSI neuron may require relatively large areas of silicon.…”

Section: A Low-powermentioning

confidence: 99%

A Systematic Method for Configuring VLSI Networks of Spiking Neurons

et al. 2011

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An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems. An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electr...

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Silicon Neurons

2014

Event‐Based Neuromorphic Systems

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Low power integrate and fire circuit for data conversion

Cited by 11 publications

References 9 publications

FRI-TEM: Time Encoding Sampling of Finite-Rate-of-Innovation Signals

FRI-TEM: Time Encoding Sampling of Finite-Rate-of-Innovation Signals

A Systematic Method for Configuring VLSI Networks of Spiking Neurons

Silicon Neurons

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