Low-power high-speed ECL circuit with 0.5- mu m rule and 30-GHz f/sub T/ technology

Abstract

An o p t i m i z a t i o n of advanced s e l f -a l i g n e d t r a n s i s t o r s f o r a low-power ECL c i r c u i t has been s t u d i e d . The ECL c i r c u i t h a s been f a b r i c a t e d with t h e 0.5-pm r u l e and a 30-GHz fT technology and has been e v a l u a t e d i n terms of t h e p r o p a g a t i o n d e l a y t i m e of r i n g o s c i l l a t o r s and a 1 / 8 s t a t i c d i v i d e r . W e have obtained 39-ps/1.6-mW ECL c i r c u i t and 12.5-GHz 1 / 8 s t a t i c d i v i d e r . I n t r o d u c t i o n B i p o l a r ECL LSIs a r e t h e components i n h i g h p e r f o r m a n c e d i g i t a l s y s t e m s s u c h a s m a i n f r a m e c o m p u t e r s a n d b r o a d b a n d t r a n s m i s s i o n systems. Today, ECL performance i s sub-100 p s i n 10K-gate V L S I s ( 1 ) . However, t h e demand f o r h i g h e r s p e e d and l a r g e r i n t e g r a t i o n i s i n c r e a s i n g , while t h e power d i s s i p a t i o n has not changed much because of t h e c o o l i n g problem. I n t h i s work, we have s t u d i e d t h e o p t i m i z a t i o n Analysis of ECL c i r c u i t The p r o p a g a t i o n d e l a y t i m e of an ECL c i r c u i t can be expressed a s t h e summation of t h e v a r i o u s CR t i m e c o n s t a n t s . A t o F : Ccb : Cbe : Csub: CL : r e : RL : P r o p o r t i o n a l i t y c o n s t a n t s Collector-base junction capacitance Base-emitter junction capacitance Cje + d i f f u s i o n capacitance Cdk C o l l e c t o r -s u b s t r a t e junction capacitance P a r a s i t i c capacitance of pull-up r e s i s t o r and i n t e r c o n n e c t i o n Base r e s i s t a n c e (sum of i n t e r n a l and e x t e r n a l ) Emitter s e r i e s r e s i s t a n c e Re + d i f f e r e n t i a l r e s i s t a n c e kT/qIc Pull-up r e s i s t o r value of ECL c i r c u i t The propagation d e l a y time of a low-power ECL c i r c u i t made by t h e conventional ESPER process has been analyzed with S P I C E c i r c u i t s i m u l a t o r b a s e d on e q u a t i o n 1 t o f i n d which t i m e c o n s t a n t p l a y s t h e most s i g n i f i c a n t r o l e i n determining t h e delay time ( F i g . 1 ) . The power CH2771-4/89/0000(0169)$1 .OO @ 1989 IEEE T -1 d i s s i p a t i o n of t h e ECL g a t e was s e t t o 1 . 6 mW. I t i s found t h a t 4 1 % of t h e d e l a y time i s due t o t h e t i m e c o n s t a n t Ccb(RL+re) and 28% t o C b e r e . T o improve t h e d e l a y t i m e , i t i s e f f e c t i v e t o r e d u c e t h e s e t i m e c o n s t a n t s . Among t h e s e parameters, RL and r e a r e of f i x e d v a l u e s determined by t h e switching c u r r e n t of t h e I n forward b i a s c o n d i t i o n , Cdk r a t h e r than Cje i s a dominant f a c t o r . T h e r e f o r e , s m a l l e r dimensions and h i g h e r c u t -o f f frequency ( f T ) must be r e a l i z e d t o o b t a i n lower Ccb and Cbe. Process designCcb has been reduced by minimizing t h e base r e g i o n with t h e 0.5-pm d e s i g n r u l e . The t r a n s i...