Low power, high resolution CMOS variable-delay element

Mourabit, Aimad El; Lu, Guo‐Neng; Pittet, Patrick; Birjali, Youness; Lahjomri, F.

doi:10.1016/j.aeue.2011.10.006

Cited by 9 publications

(8 citation statements)

References 7 publications

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“…In this case, all of the computation units can be realized by very few adders, as shown in Figure 6. The maximum number of α needs to be (n + 1)/2 − 1, which is the ratio of medium and fine resolution in Equation (5). The maximum number of β and γ is n − 1 and 2 K − 2M + 1 , respectively.…”

Section: Circuit Description Of 3d Vernier Dtcmentioning

confidence: 99%

“…A digital-to-time converter (DTC) is used to generate a time signal with a width that is proportional to the programmable input digital value. It has been widely used in the fields of automatic test equipment (ATE) or measurement instruments [1][2][3][4][5][6][7][8][9][10][11][12]. High resolution is the most critical consideration in DTC design, which means high precision and high performance of ATE and measurement instruments.…”

Section: Introductionmentioning

confidence: 99%

“…High resolution is the most critical consideration in DTC design, which means high precision and high performance of ATE and measurement instruments. In terms of implementing methods, the DTCs can be classified as application specific integrated circuit (ASIC) DTC [1][2][3][4][5][6][7]9] and field programmable gate arrays FPGA-DTC [6,8,11]. The resolution of ASIC-DTCs can be better than 1 ps, which is realized with the capacitor charging circuit.…”

Section: Introductionmentioning

confidence: 99%

“…But the ASIC-DTCs are limited by small dynamic range, high cost and long development time. The DTCs also can be classified with absolute [1][2][3][4][5][6][7]12] or relative [8][9][10][11] time generation due to different operations. The absolute time generations have wide dynamic ranges but poor resolution performance.…”

Section: Introductionmentioning

confidence: 99%

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A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

Yan

2019

Applied Sciences

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In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretical fine resolution of the proposed DTC is improved by calculating the period difference two times. The achieved resolution of the proposed DTC is 203 fs realized with an Altera Stratix III FPGA chip, which is about tenfold higher than traditional FPGA-DTC implemented with the same series FPGAs. The worst absolute differential nonlinearity (DNL) and integral nonlinearity (INL) are verified smaller than 0.88 least significant bit (LSB) and 4.4 LSB, respectively. By optimized computation logic, there are only 448 adaptive look-up-tables (ALUTs), 237 registers and three phase locked loops (PLLs) utilized for circuit implementation. Experimental results prove that the proposed DTC features high resolution with low cost.

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Section: Circuit Description Of 3d Vernier Dtcmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

Yan

2019

Applied Sciences

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“…The drive strength can be changed through two main methods which are changing the power supply voltage, also called supply modulation (Nuyts et al 2014 ; Klepacki et al 2014 ; Yang 2003 ), and current-starving (Schidl et al 2012 ; Nuyts et al 2014 ; Klepacki et al 2014 ). The current-starving method can be implemented using many techniques, but the main are: adding delay-controlling MOS transistors of controlled aspect ratio which act as adjustable current sources at the pull down and/or pull up networks (Maymandi-Nejad and Sachdev 2005 ; Klepacki et al 2014 ; Henzler 2010b ; Rahkonen and Kostamovaara 1993 ), connecting additional delay-controlling MOS transistors at the output of logic gates as in the case of a transmission gate placed at the output of a logic gate (Nuyts et al 2014 ; Mahapatra et al 2002 ), employing a neuron-MOS mechanism which is based on an nMOS transistor with a gate electrode electrically floating (Zhang and Kaneko 2015 ; Shibata and Ohmi 1992 ), and employing an RC-based differentiator to drive the pMOS transistor of a CMOS inverter (El Mourabit et al 2012 ).…”

Section: Analog-tunable Delay Elementsmentioning

confidence: 99%

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

et al. 2016

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A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

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