Low Power GaAs Digital and Analog Functionalities for Microwave Signal Conditioning in AESA Systems

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

“…Both architectures require additional source followers and level-shifting diodes, thus making the circuit very complex and hence not well suited for highly integrated MMICs [22]. On the contrary, if a differential approach is exploited at flip-flop level, adopting a differential flip-flop structure driven by both true and complementary data and clock signals, an optimum trade-off among noise margin, transistor count and power consumption can be achieved [15,18,39]. For more details on the various logic families, the reader can refer to [9,14,22,33] and references therein.…”

“…Another issue, highlighted in [15,39], is that PDKs model typically does not allow interchanging the role of drain and source terminals, i.e., the model is asymmetrical. In some cases, e.g., in processes with field plate, this asymmetry is mandatory, but more often is just added for convenience, since in microwave circuits the role of these two terminals is always distinct and defined a priori (even, in some models the source terminal is internally grounded and not available to the user).…”

“…This comes at the price of larger occupied area and possibly increased power consumption, hence requiring careful optimization. The works reported in [15,18,39] exploit a differential MS (D-MS) flip-flop composed of two identical D-type latches of the kind reported in Figure 7d. Thanks to the pseudo-open drain nature of the NAND ports, the total transistor count is kept relatively low: only 12 transistors, excluding that/those for complementary clock generation and in case of E-DCFL implementation, instead of the 16 required with the classical latch structure of Figure 7b (or Figure 7c).…”