Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint

Chiu, Po-Xun; Lin, Ying‐Chih; Hsieh, Yi‐Ling; Hsieh, Tsai-Ming

doi:10.1109/iscas.2001.922099

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

DOI: 10.1109/iscas.2001.922099

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Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint

Po-Xun Chiu

Ying‐Chih Lin²,

Yi‐Ling Hsieh³

et al.

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Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint

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References 9 publications

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