Low power design practices for power optimization at the logic and architecture levels for VLSI system design

Chakraverty, Mayank; Ps, Harisankar; Ruparelia, Vaibhav

doi:10.1109/iceets.2016.7583845

Cited by 10 publications

(2 citation statements)

References 9 publications

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“…Over 80% of the power is consumed by digital circuit in deep sleep mode which is the common state for most devices in a low-power system. Considering the fact that transistors with different Vth levels are incorporated in building the digital circuits, an optimized balance between the performance and leakage can be achieved by properly assigning FET with higher Vth for better leakage and lower Vth for better performance [8][9][10] . The leakage current level dominated by the channel and gate leakage current under turn-off state further determines the static power consumption [11][12][13] .…”

Section: Introductionmentioning

confidence: 99%

Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

Zhao

Zhou

Zhu³

et al. 2021

IEEE J. Electron Devices Soc.

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The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultrahigh Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimization to minimize the gate leakage current towards low-power MCU applications. Based on the 55 nm node, it has been found both theoretically and experimentally that the leakage level has been significantly reduced at different temperature in n-FET, p-FET, data flip-flop (DFF) and inverter (INV). Upon MCU testing under active, sleep and deep sleep modes, obvious decrease in the power consumption is also achieved, providing a promising optimization approach towards a better balance between the speed and power in modern MCU technology.

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Section: Introductionmentioning

confidence: 99%

Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

Zhao

Zhou

Zhu³

et al. 2021

IEEE J. Electron Devices Soc.

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“…Architectural level optimization refers to those techniques that are decided while coding the system, in other words they are the RTL level techniques. Logic level techniques are those which are applied at the logic level by optimization of the logic components either by improving their implementation logically of by removing redundant logic [3]. Circuit level techniques are those applied at the circuit and transistor levels.…”

Section: Introductionmentioning

confidence: 99%

Clock Power Optimizations in VLSI design at Advanced Technology Nodes

Rao¹,

Aradhya²

2017

IJCA

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Power reduction in VLSI designs is one of the key design constraints along with others, namely timing, area, quality constraints, noise, etc. Even though there has been a steady growth of devices that are able to be placed in a given area of a chip as per Moore's law, the same cannot be said for battery technologies as they have never been able to catch up. Since the advent of the deep sub-micron era, speed and higher frequency of operation have become the prime goals of any design as the hunger for faster and better optimized systems are never ending. But as a consequence of faster operating speeds which basically means higher clock frequencies, power becomes one of the main constraints to be considered as the most important component of power dissipation, namely the dynamic power dissipation has a proportional relationship with the clock frequency. Hence clock power optimization is taken up as the prime objective of this paper for technologies below 14 nm as at these technologies, other secondary power dissipation components start to become more prominent. Various design techniques have been discussed and applied at both the circuit design and the RTL levels of abstraction in order to provide a complete review of most of the low power design techniques which can be used to reduce power at both these levels of abstraction. An improvement of 25% and 15.7% of power reduction are observed in clock power and overall power respectively. There is also a power reduction of 2-5% for each of the RTL level optimization techniques. General TermsClock power optimization, Moore's law, Deep sub-micron era, Levels of abstraction.

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