Low power design of signal processing systems using characterization of silicon IP cores

Keane, G.; Spanier, Jonathan Robert; Woods, Roger

doi:10.1109/acssc.1999.832432

Cited by 4 publications

(3 citation statements)

References 27 publications

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“…The use of highly pipelined circuit architectures is particularly applicable to DSP-based FPGA implementations as FPGAs possess plentiful supplies of available registers and therefore allow considerable speed improvements over non-pipelined equivalent designs. It has also been demonstrated that pipelining provides reductions in dynamic power consumption [32,33] due to a reduction in capacitance and switching activity. The use of completely synchronous systems however, is limited to the SoC block level as asynchronous interconnection technologies begin to dominate inter-block communication [34].…”

Section: Future Challengesmentioning

confidence: 98%

From Bit Level Systolic Arrays to HDTV Processor Chips

Woods¹,

McCanny²,

McWhirter

2007

J Sign Process Syst Sign Image Video Technol

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The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on^algorithmic engineering^and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology.

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Section: Future Challengesmentioning

confidence: 98%

From Bit Level Systolic Arrays to HDTV Processor Chips

Woods¹,

McCanny²,

McWhirter

2007

J Sign Process Syst Sign Image Video Technol

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show abstract

“…In addition to providing the speed-up, pipelining provides a highly useful mechanism to reduce power consumption (Raghunathan 1999, Keane et al 1999, particularly in FPGA (Wilton et al 2004). In FPGA designs, the aim of the place and route tools is to achieve the best placement in order to achieve the required speed (and more recently, power-efficient realization).…”

Section: Pipeliningmentioning

confidence: 99%

“…As was demonstrated in the pipelining example in the previous section, an architectural optimization can bring benefits in terms of reduced power consumption. The work of Keane et al (1999), showed clearly how creating architectures, in this case bit-level architectures for multipliers, could provide reduced power consumption. The comparison was based on ASIC, but the key message from the paper was the importance of preserving locality.…”

Section: Localitymentioning

confidence: 99%

Final Statements

2008

FPGA‐Based Implementation of Signal Processing Systems

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Designations used by companies to distinguish their products are often claimed as trademarks. All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners. The publisher is not associated with any product or vendor mentioned in this book. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold on the understanding that the publisher is not engaged in rendering professional services. If professional advice or other expert assistance is required, the services of a competent professional should be sought. Library of Congress Cataloging-in-Publication DataWood, Roger.FPGA-based implementation of complex signal processing systems / Roger Wood ... [et al.]. p. cm. Includes bibliographical references and index.

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Low-power synthesis flow for regular processor design

Woods

Lightbody²,

Cassidy³

et al. 2001

IEE Seminar Low Power IC Design

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The paper presents the development of a low-power synthesis flow for the development of dedicated silicon circuits fbr data-dominated applications such as DSP systems. The work was carried out as part of a European ESPRIT low power action and a collaborative "low-power" project involving the universities of Liverpool, Manchester and Sheffield The design flow is briefly d e s m i and some results are presented for mult~~lier implementations and their use m the development of a Discrete Cosine Transform (DCT) circuit

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Low power design of signal processing systems using characterization of silicon IP cores

Cited by 4 publications

References 27 publications

From Bit Level Systolic Arrays to HDTV Processor Chips

From Bit Level Systolic Arrays to HDTV Processor Chips

Final Statements

Low-power synthesis flow for regular processor design

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