Low-power design methodology for DSP systems using multirate approach

Wu, An-Yeu; Liu, K.J.R.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, A.

doi:10.1109/iscas.1996.541959

Cited by 18 publications

(16 citation statements)

References 6 publications

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“…The dynamic power consumption of a CMOS circuit is given by (17) where is the average fraction of the total node capacitance being switched (also referred to as the activity factor), is the total switching capacitance, is the supply voltage and is the clock frequency. By employing (17), we get the ratio of the power consumption of two-stage look-ahead design, , to the power of original design, , as V V where is the original operating frequency, and represent the total switching capacitances of look-ahead and its original implementation.…”

Section: Substitutingmentioning

confidence: 99%

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Low-power architectures for compressed domain video coding co-processor

Chen¹,

Liu

2000

IEEE Trans. Multimedia

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Low power as a de facto is one of the most important criteria for many signal-processing system designs, particularly in multimedia cellular applications and multimedia system on chip design. There have been many approaches to achieve this design goal at many different implementation levels ranging from very-large-scale-integration fabrication technology to system design. In this paper, the multirate low-power design technique will be used along with other methods such as look-ahead, pipelining in designing cost-effective low-power architectures of compressed domain video coding co-processor. Our emphasis is on optimizing power consumption by minimizing computational units along the data path. We demonstrate both low-power and high-speed can be accomplished at algorithm/architecture level. Based on the calculation and simulation results, the design can achieve significant power savings in the range of 60%-80% or speedup factor of two at the needs of users.Index Terms-Compressed domain video coding, DCT, low-power architecture, motion estimation.

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Section: Substitutingmentioning

confidence: 99%

“…The multirate low-power design technique [16], [17] will be used along with other low-power design methods such as look-ahead, pipelining in our design to achieve low-power/high-speed performance. In what follows, we explain the detailed design of our compressed domain low-power video coding co-processor.…”

Section: Introductionmentioning

confidence: 99%

Low-power architectures for compressed domain video coding co-processor

Chen¹,

Liu

2000

IEEE Trans. Multimedia

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“…Let EXAMPLE_DSP be a digital signal pro.cessing algorithm requiring evaluation of 4-point inner products between 4-point data and coefficient vectors. Let the coefficient vector [Co, Ca, c2, c3] be equal to [13,2,9, 6] and assume that the data vector [do, d1, d2, d3] at a specific instance of the algorithm is equal to [1,3,14,2]. EXAMPLE_DSP requires computation of 4-point inner products y using the following equation:…”

Section: Motivating Examplementioning

confidence: 99%

“…In [11, 12] low power architectures for the Discrete Cosine Transform (DCT) and the Discrete Fourier Transform (DFT) are presented respectively. General methodologies for low power digital signal processing are described in [13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

Masselos¹,

Merakos²,

Stouraitis³

et al. 1998

VLSI Design

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A novel architectural transformation for low power synthesis of inner product computational structures is presented. The proposed transformation reorders the sequence of evaluation of the multiply-accumulate operations that form the inner products. Information related to both coefficients, which are statically determined, and data, which are dynamic, is used to drive the reordering of computation. The reordering of computation reduces the switching activity at the inputs of the computational units but inside them as well leading to power consumption reduction. Different classes of algorithms requiring inner product computation are identified and the problem of computation reordering is formulated for each of them. The target architecture to which the proposed transformation applies is based on a power optimal memory organization and is described in detail. Experimental results for several DSP algorithms show that the proposed transformation leads to significant savings in net switching activity and thus in power consumption.

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“…This paper proposes a parallel context-modeling scheme based on the PPCM technique to generate several CX-D data each cycle, and a matched pipelined MQ-coder is designed to accomplish a high-performance Tier-1 coder. Since the EBCOT encoder takes most of the computation time, our proposed parallel context-modeling architecture can further be applied to the multirate approach [14] to reduce the power consumption.…”

Section: Introductionmentioning

confidence: 99%

High Efficiency EBCOT with Parallel Coding Architecture for JPEG2000

Chiang

Chang

Hsieh

et al. 2006

EURASIP J. Adv. Signal Process.

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This work presents a parallel context-modeling coding architecture and a matching arithmetic coder (MQ-coder) for the embedded block coding (EBCOT) unit of the JPEG2000 encoder. Tier-1 of the EBCOT consumes most of the computation time in a JPEG2000 encoding system. The proposed parallel architecture can increase the throughput rate of the context modeling. To match the high throughput rate of the parallel context-modeling architecture, an efficient pipelined architecture for context-based adaptive arithmetic encoder is proposed. This encoder of JPEG2000 can work at 180 MHz to encode one symbol each cycle. Compared with the previous context-modeling architectures, our parallel architectures can improve the throughput rate up to 25%.

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Low-power design methodology for DSP systems using multirate approach

Cited by 18 publications

References 6 publications

Low-power architectures for compressed domain video coding co-processor

Low-power architectures for compressed domain video coding co-processor

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

High Efficiency EBCOT with Parallel Coding Architecture for JPEG2000

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