Low-power design-for-test implementation on phase-locked loop design

Abstract

Low-power design for test is the need of the hour for any system-on-chip designer. The low-power design techniques have been a major challenge to both the designer as well as the testing engineer. With so many advancements in low-power technology in the phase of register transfer logic design, functional verification, register transfer logic and physical synthesis and physical design. Design for test is not an exception to this. The low-power design-for-test techniques can be applied at various levels of the design-for-test flow as in the scan insertion stage, automatic test pattern generation simulations stage, testing stage, and so on. Some of the reasons for the high-power utilization in the design-for-test phase can be due to the external circuitry being inserted during the design phase and not used in the functional mode. The complete circuit will be active in the test mode only. In this paper, the focus will be primarily on reducing the power during the automatic test pattern generation scan synthesis phase. All the scan flops are connected by a common scan clock with a fixed frequency. The intention of this study is to divide the clock frequency by half and make sure that the power is reduced without affecting any timing violations. Since the scan clock frequency is low, it can be further divided to ensure that power is reduced without affecting the testing process of the chip.

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