Low power design for speech codec

Okamura, T; Kinoshita, Y.; Yoshida, Hayato; Yamane, D.

doi:10.1109/asic.1998.722818

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“…[6] and [7] describe processors which provide a customized instruction set, whilst [Sldescribes an FPGA implementation.…”

Section: Introductionmentioning

confidence: 99%

A low power datapath for algebraic codebook search targeting a generic GSM system-on-chip platform

Kirkham

Arslan

Westall³

et al.

Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)

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A novel hardware architecture is presented for the Algebraic Codebook Search function wed in GSM Adaptive Multi-Rate speech encoding. This architecture was for a System-on-Chip GSM baseband processing platform and is an accelerator for use with a programmable DSP Intellectual Property Core. Features of the algorithm are exploited to achieve an efficient hardware-software partitioning. The over all effect is a 5x reduction in power consumption and a 28% reduction in MIPS.

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“…[6] and [7] describe processors which provide a customized instruction set, whilst [Sldescribes an FPGA implementation.…”

Section: Introductionmentioning

confidence: 99%