Low power data decision IC for 20–40 Gbit/s data links using 0.2 [micro sign]m AlGaAs/GaAs HEMTs

Wang, Z.-G.; Berroth, Manfred; Thiede, A.; Rieger-Motzer, M.; Hofmann, Peter; Hulsmann, A.; Kaufel, G.; Köhler, K.; Raynor, B.; Schneider, J.

doi:10.1049/el:19961241

Cited by 10 publications

(4 citation statements)

References 2 publications

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“…Other circuit configurations, like a parallel feedback amplifier and a source follower with a bypass capacitor, are employed to enlarge the bandwidth of input buffers. 26,31 The data buffer shown in Fig. 10 was also used as an output buffer in our HFET ICs.…”

Section: Digital Icsmentioning

confidence: 99%

Present Status and Future Prospects of High-Speed Lightwave Ics Based on Inp

Sano

Hagimoto

Ishii

1998

Int. J. Hi. Spe. Ele. Syst.

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High-speed integrated circuits (ICs) are essential for expanding the capacity of lightwave communications. InP-based heterostructure field effect transistors (HFETs) and heterojunction bipolar transistors (HBTs) are very promising for producing high-speed digital and analog ICs. This paper reviews the current status of InP-based lightwave communication ICs in terms of device, circuit, and packaging technologies. A successful 40-Gbit/s, 300-km optical fiber transmission using InP HFET ICs demonstrates the feasibility of the ICs. Furthermore, we estimate future IC performance based on the relationship between electron device figures-of-merit and IC speed. To keep up with the performance trend, technological problems, like inter-and intra-chip interconnections, have to be solved. Int. J. Hi. Spe. Ele. Syst. 1998.09:567-593. Downloaded from www.worldscientific.com by UNIVERSITY OF QUEENSLAND on 02/03/15. For personal use only. Transmitter Receiver 2D.

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Section: Digital Icsmentioning

confidence: 99%

Present Status and Future Prospects of High-Speed Lightwave Ics Based on Inp

Sano

Hagimoto

Ishii

1998

Int. J. Hi. Spe. Ele. Syst.

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“…16 The parallel data decision simultaneously forms the first stage of demultiplexing. 17 We constructed 1:2, 2:4 as well as 1:4 demultiplexer circuits that have achieved a 40 Gbit/s bit rate. The 1:4 demultiplexer chip comprises about 420 active elements, an area of 1.5 x 1.5 mm 2 , and a power consumption of 1.6 W. 12 Recent development has been driven to integration of 40-Gbit/s clock recovery, data decision, and demultiplexing.…”

Section: Fiber Optic Data Transmission Systemsmentioning

confidence: 99%

HIGH FREQUENCY CIRCUITS BASED ON GaAs PHEMT TECHNOLOGY FOR MODERN SENSOR AND COMMUNICATION SYSTEMS

Schlechtweg

2000

Int. J. Hi. Spe. Ele. Syst.

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For sensor and communication system applications, monolithic microwave integrated circuits (MMICs) feature performance, functionality, reliability, and competitive price. In this paper, the potential of PHEMT ICs for communication and sensor applications up to 100 GHz is discussed. Specifically, I will address the application of coplanar waveguide technology for rf ICs, millimeter-wave multifunctional ICs and power amplifiers, as well as mixed-signal ICs and OEICs. A 77-GHz transceiver MMIC designed for automotive collision avoidance radar is presented as an example of a very compact, multifunctional mm-wave chip. A chip set for active and passive imaging at 94 GHz includes low noise and high gain amplifiers, low phase noise oscillators, and phase shifters. An FMCW module is conceived for material characterization. A family of coplanar power amplifier MMICs for wireless communication in the range of 20 to 60 GHz with output powers up to 1 W is presented. Finally, integrated circuits for high-speed data transmission at 40 Gbit/s will be discussed. Int. J. Hi. Spe. Ele. Syst. 2000.10:393-411. Downloaded from www.worldscientific.com by MONASH UNIVERSITY on 02/03/15. For personal use only.

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“…To meet these demands, higher-level of Synchronous Digital Hierarchy (SDH), such as STM-1 6 at 2.5 GbIs, has been used for the backbone network. However, most high-speed circuits of system are realized using 111-V or silicon bipolar technologies [1][2]. As CMOS technology continues to benefit from both scaling-down and the enormous momentum of the digital market, many high-speed ICs are likely to appear as CMOS low-cost implementations now [3][4].…”

Section: Introductionmentioning

confidence: 99%

“…Another realization of a holder is to use a latch or flip-flop circuit. Integrated decision circuits are most composed ofdata flip-flops (D-FF) [5].A Master-Slave D-FF (MS-DFF) in Source Coupled FET logic (SCFL) was used to build the decision circuit[2], as shown inFig. 1andFig.2.…”

mentioning

confidence: 99%

3.5-Gb/s 0.35-μm CMOS data decision IC

Wang

et al. 2001

Fiber Optics and Optoelectronics for Network Applications

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A data decision IC is designed for STM-16 SDH-systems. A differential high-speed master-slave DFF is used for the decision function. Wide-band high-gain amplifiers are used for input and output data buffers to obtain high sensitivity and sufficient drive capability. The chip was realized in a O.35-tm CMOS foundry technology. The chip size is 0.7 X 0.8mm2.The supply voltage is 5 V and the current is 50 mA. A working data rate of higher than 3.5Gb/s has been measured. The sensitivity is as low as 10--20mV.

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Low power data decision IC for 20–40 Gbit/s data links using 0.2 [micro sign]m AlGaAs/GaAs HEMTs

Cited by 10 publications

References 2 publications

Present Status and Future Prospects of High-Speed Lightwave Ics Based on Inp

Present Status and Future Prospects of High-Speed Lightwave Ics Based on Inp

HIGH FREQUENCY CIRCUITS BASED ON GaAs PHEMT TECHNOLOGY FOR MODERN SENSOR AND COMMUNICATION SYSTEMS

3.5-Gb/s 0.35-μm CMOS data decision IC

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