Low‐power consumption ternary full adder based on CNTFET

Abstract

This paper presents low-power circuits to implement ternary full adder (TFA) using carbon nanotube field-effect transistors (CNTFETs). Besides the unique characteristics of the CNTs, the threshold voltage simple control is the best property to implement ternary logic circuits. Low-complexity, low-power consumption and low-power delay product (PDP) are the benefits of the proposed circuits in comparison with all previous presented designs of TFA. The final proposed TFA is robust and has proper noise margins. The structure of the final proposed TFA is more appropriate to use in ripple adders, since the first ternary half sum generators (THSGs) in all cells produce their outputs in parallel (in the final proposed TFA, the output of the first THSG of the sum-generation unit is also used in the carry-generation unit). The proposed circuits are simulated using HSPICE with 32 nm-CNTFET technology. According to simulation results, the final proposed TFA has reduced the power consumption significantly and results in 86.92 and 97% reductions in terms of the PDP in comparison with two recent proposed designs.

Cntfet Based Novel 14t Adder Cell for Low Power Computation

“…Moreover, SB-CNTFETs are ambipolar. In ohmic contact heavily doped source and drain are used and lock of SB in source channel causes lower off leakage current and higher on-current [1]. The IV characteristic of the ohmic contact CNTFET is similar to the MOSFET.…”

“…3,Vπ = 3.033 eV is the carbon π-π bond energy in the tight bonding model, e is the unit electron charge and DCNT is the CNT diameter as per Eq. (1), the threshold voltage of the CNTFET is inversely related to the nanotube diameter [1].…”

Inverter‐based, low‐power and low‐voltage, new mixed‐mode Gm‐C filter in subthreshold CNTFET technology

“…Although, using complementary metal-oxide semiconductor (CMOS) technology was a good candidate for designing of microelectronic chips in the past decades, however, employing new emerging technologies in the nanometre scale seems inevitable in the near future, due to the growing problems with CMOS technology, such as limitations in the lithographic process, leakage currents and quantum confinements which appear in the shrinking down of the transistor dimensions beyond 45 nm technology [8][9][10][11].…”

“…Giving the above facts, carbon nanotube field-effect transistor (CNTFET) with metal-oxide-semiconductor field-effect transistor (MOSFET)-like behaviour provides some benefits, such as small chip size, quasi-ballistic transfer and higher mobility of carriers, improved (g m /I D ) characteristics versus normalised drain current and lower values for parasitic capacitances (that leads to a lower intrinsic delay and higher frequency bandwidth), that is a very suitable candidate for replacing the CMOS technology [9][10][11].…”

“…1 shows a typical structure of a MOSFET-like CNTFET in which the semiconducting nanotubes are placed under the gate terminal as the channel region, while the doped CNTs are placed between the gate and source/drain terminals to realise a low 'ON resistance'device. However, by changing the gate potential, the CNTFET device turns on/off electrostatically, similar to conventional MOSFET devices [9][10][11]. Table 1 introduces the physical parameters of a CNTFET device and their typical values.…”