Low-power column-parallel ADC for CMOS image sensor by leveraging spatial likelihood in natural scene

Abstract

Column-Parallel analog-to-digital converter (ADC) technology has often been integrated in CMOS Image Sensors as a system-on-chip (SoC) solution, in particular for portable devices. Since the power consumption of column-parallel ADCs in CMOS image sensors play an important role in total power consumption, a low-power application on has been developed specifically for integration in low-power image systems.In a conventional column-parallel ADC design, the ADC operation is repeated row to row, column to column and frame to frame, regardless of the properties of the scenes.In this thesis, a new operating method is proposed, which takes into account spatial likelihood in natural scenes. In the proposed method, the MSBs of selected pixel would be predicted before the ADC operation, based on that pixel's neighbor pixels in the previous row. Because there is strong correlation between consecutive rows in most natural scenes, pre-ADC pixel estimation could save bits in ADC conversion cycles. The total number of ADC conversions would effectively be reduced, resulting in lower power consumption. This method was verified in extensive Matlab simulations, where ADC conversion cycles were reduced by up to 20%-30% for most natural scenes and a saving of up to 29.49% was achieved in switching energy for a 512×512 resolution Lena image. This thesis presents the design of a column-parallel low-power ADC system for a CMOS image sensor with the proposed algorithm. The system was implemented in AMS 0.35 µm CMOS technology. The study also details the simulation of the algorithm and the testing of the hardware. Improvements made to the algorithm after the analysis and testing of the CMOS imaging sensor are described at the end of the thesis. i I would like to express my sincerest gratitude to my Master program supervisor, Professor Chen Shoushun, for his insight of IC design, his research methodology and inspiring thinking, his steady encouragement and guidance throughout my two-year master study. The supervision and the systematic training provided by him really helped me on exploring out the system-level design of an image sensor and critical thinking on both top level and circuit level. Besides, I am really appreciate his trust on my research working and my working ability. I would also like to thank my seniors in this sensor group, Dr. Yuan Chao, Mr. Qian Xinyuan, Mr. Ding Ruoxi, Mr. Zhang Xiangyu for their assistance on brainstorm, continuous design review and the continuous help on image sensor testing. I want to give my special thanks to my another senior, Mr. Yu Hang, a research fellow in this sensor group, for his patiently guidance and meaningful suggestion given during my chip design.Lastly, I want to thank all of my friends, their friendship really make my two-year study be interesting, meaningful and special.

A Low-Power CMOS Image Sensor With Multiple-Column-Parallel Readout Structure

“…This means that when the proposed LBC scheme is applied in high-resolution CISs, the PSE would be greater because the power consumed by the pixel SF is comparatively higher. Referring to (10), when the proportion of T A/D increases as the ADC resolution increases, the proposed LBC scheme can be used more effectively for high-resolution ADCs. Considering these, although the proposed LBC scheme was verified in this study for the prototype CIS with low pixel resolution, it is worth noting that the PSE of the LBC scheme is expected to increase further when applied for high pixel resolution in high-resolution ADCs.…”

“…Considering that the proportion of T A/D increases as the ADC resolution increases, the proposed LBC scheme can be used more effectively for high-resolution ADCs in the MCP readout structure, as observed from (10). In particular, its efficiency would be greater in a low-power CIS, where the power consumption of the pixel SF is comparatively higher.…”

“…Various studies have been reported on low-power circuit design [5]- [7] in literature for specific operating conditions. In addition, low-power readout techniques that are optimized for the characteristics of input signals [8]- [10] and specific operations related to applications [11]- [14] have been reported. For example, Park et al [7] achieved low power consumption by adopting a fully dynamic CIS structure; however, this structure is not suitable for high-speed operation because it suffers from high readout noise due to increased global supply signal and power-line fluctuations.…”

“…For example, Park et al [7] achieved low power consumption by adopting a fully dynamic CIS structure; however, this structure is not suitable for high-speed operation because it suffers from high readout noise due to increased global supply signal and power-line fluctuations. Liu et al [10] used pixel signal similarity to implement a low-power readout scheme by reusing the conversion results of previous pixels; however, this scheme is difficult to apply to a readout structure that shares a global reference for analog-to-digital (A/D) conversion. Kim et al [13] proposed a multiresolution CIS adopting the subsampling method to optimize power consumption depending on the imaging conditions; however, the sizes of logic circuits for multiresolution imaging increase with pixel resolution reduction ratios.…”