Low Power Asynchronous Circuit Design: An FFT/IFFT Processor

Gwee, Bah-Hwee; Chong, Kwen-Siong

doi:10.1007/978-90-481-9216-8_3

Cited by 1 publication

(1 citation statement)

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“…Lower power consumption thanks to data-driven operation, lower EMI, possibility of dynamic voltage scaling, the ability of withstanding harsh environment and many more. However, the drawbacks of asynchronous digital systems include the immaturity of the methodology itself, lack of professional design CAD tools, difficulties with testing and higher requirements of the circuit area due to more complex controlling block [3]. As we mentioned before, asynchronous circuits, sometimes referred to as self-times or clock-less circuits, exhibit better performance at the cost of sacrificing the circuit area.…”

Section: Introductionmentioning

confidence: 96%

Design of a globally asynchronous locally synchronous digital system

Nagy

Koscelansky

Stopjaková

2014

2014 IEEE 12th IEEE International Conference on Emerging eLearning Technologies and Applications (ICETA)

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The article addresses a design methodology of globally asynchronous locally synchronous (GALS) digital systems from the designer's point of view. It discusses the nature of this special type of electronic circuits, its advantages as well as drawbacks as comparison to standard synchronous and asynchronous systems. Furthermore, it describes the top-down design flow for various implementation approaches. The first one is the implementation onto silicon chip as ASIC, the second one is the implementation into the FPGA. The paper also discusses the comparison of three different implementations of the same circuitry.

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Section: Introductionmentioning

confidence: 96%