Low power/area branch prediction using complementary branch predictors

Sendag, Resit; Yi, Jiangfang; Chuang, Peng-fei; Lilja, David J.

doi:10.1109/ipdps.2008.4536323

Cited by 5 publications

(11 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Sendag et al 49 The overall BP design proposed by Lai et al 95 It has a primary BP and three correctors: an interval corrector, a bimodal corrector, and a two-level corrector loop-exit, eg, due to the break instruction. The "branch misprediction predictor" can work with any BP.…”

Section: Predicting Loop-exit Branchesmentioning

confidence: 99%

A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

View full text Add to dashboard Cite

Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers. KEYWORDSdynamic branch predictor, hybrid BP, neural BP, perceptron predictorside BP, pipelining, predictor accuracy, review, side BP, speculative execution, two-level BP INTRODUCTIONControl-changing instructions such as branches add uncertainty in the execution of dependent instructions and thus lead to large performance loss in pipelined processors. To offset their overhead, accurate prediction of branch outcomes is vital. Since branch misprediction incurs high latency (eg, 14 to 25 cycles 1 ) and wastes energy due to execution of instructions on wrong-path, an improvement in BP* accuracy can boost performance and energy efficiency significantly. For example, experiments on real processors showed that reducing the branch mispredictions by half improved the processor performance by 13%. 2Effective design and management of BPs, however, presents several challenges. Design of BP involves a strict tradeoff between area, energy, accuracy, and latency. An increase in BP complexity for improving accuracy may make it infeasible for implementation or offset its performance benefit. For example, a 512 KB perceptron predictor may provide lower instruction-per-cycle than its 32 KB version, 3 and a 2-cycle fully accurate BP may provide lower instruction-per-cycle than a 1-cycle partially inaccurate BP. 4 Further, due to its high access frequency, BP becomes a thermal hot-spot, 5 and hence, reducing its dynamic and leakage energy is important. Clearly, intelligent techniques are required for resolving these issues.Further, recently, researchers have demonstrated two security vulnerabilities viz., "Meltdown" and "Spectre," which exploit speculative execution feature of modern CPUs. 6-8 For example, Spectre vulnerability works on the observation that the speculative execution due to a branch misprediction may leave side effects, which can reveal sensitive data to attackers, eg, if the memory accesses performed during speculative execution depends on sensitive data, the resulting state of the cache forms a side-channel through which the sensitive data can be leaked. These vulnerabilities affect nearly every modern CPU. While avoiding speculative execution (eg, disabling branch prediction) can mitigate these vulnerabilities, it leads to significant performance loss. In light of these vulnerabilities and associated tradeoffs, a deeper study of branch predictors is definitely required. Contributions:In this ...

show abstract

Section: Predicting Loop-exit Branchesmentioning

confidence: 99%

A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…The filter part is exemplified by Sentry Table Filter [1], yet conceptually other filter methods, such as PPD [17] or NBD [25] can also be applied. The hedging part (Hedge State Machine) can adopt Complementary Branch Prediction (CBP) [18] [19] or other methods, such as the Prophet/Critic Hybrid Branch Prediction [15] [16]. In this paper, the hedging part is embodied by CBP.…”

Section: A Hedging Filter Hfmentioning

confidence: 99%

“…Complementary branch prediction or CBP [18] [19] can improve prediction accuracy and processor performance greatly with little to moderate increase in hardware cost. From an equal or slightly superior performance perspective, a smaller branch direction predictor or a branch target buffer can be adopted, which not only reduces hardware cost but also saves static power consumption substantially.…”

Section: Complementary Branch Prediction (Cbp)mentioning

confidence: 99%

Cost-effective branch prediction by combining hedging and filtering

Maa

Yen

Kuo

et al. 2010

2010 International Computer Symposium (ICS2010)

View full text Add to dashboard Cite

With the ever increasing needs of power aware architecture and circuit design in recent years, how to reduce the power consumption of processors without sacrificing performance has become an important issue. In this paper, we propose a new method for low power branch predictionHedging Filter, which combines filtering scheme reducing dynamic power consumption with hedging prediction mechanism lowering static power dissipation. We analyze and empirically study this proposed scheme embodied in the Sentry Table-Complementary Branch Prediction combo with respect to critical path delay, performance, hardware overhead and power consumption. Hedging Filter not only preserves critical path delay and prediction accuracy, but also contributes to the savings of dynamic and static power. From our evaluation, presuming equivalent or superior performance with respect to traditional counterparts, the proposed method reduces branch prediction hardware cost by up to 71% and power saving by up to 79% respectively.

show abstract

“…Bimodal은 최근의 분기 결과를 BHT (Branch History [7] . 기존의 분기 예측기는 대부분 범용 프로세서를 기준으로 설계되므로 전력 소모가 많고 분기의 예측률을 높이기 위해 노력하 였다 [8][9][10][11] . [12] .…”

unclassified

“…Gshare 분기 예측 기를 개선하기 위해 R. Sendag는 Branch BMP (Misprediction Predictor)를 두어 conflict 상황을 제 거하였고 [8] , Y. Maa는 BTAC의 주소를 Hedging하 여 접근하였다 [9] . T. Chen은 2단으로 구성된 분기 예측기를 사용하였다.…”

unclassified

An Improved Dynamic Branch Predictor by Selective Access of a Specific Element in 4-Way Cache

Hwang

2013

The Journal of Korean Institute of Communications and Informati

View full text Add to dashboard Cite

In-sung Hwang , Sun-young Hwang°요 ABSTRACTThis paper proposes an improved branch predictor that reduces the number execution cycles of applications by selectively accessing a specific element in 4-way associative cache. When a branch instruction is fetched, the proposed branch predictor acquires a branch target address from the selected element in the cache by referring to MRU buffer. Branch prediction rate and application execution speed are considerably improved by increasing the number of BTAC entries in restricted power condition, when compared with that of previous branch predictor which accesses all elements. The effectiveness of the proposed dynamic branch predictor is verified by executing benchmark applications on the core simulator. Experimental results show that number of execution cycles decreases by an average of 10.1%, while power consumption increases an average of 7.4%, when compared to that of a core without a dynamic branch predictor. Execution cycles are reduced by 4.1% in comparison with a core which employs previous dynamic branch predictor.

show abstract

Low power/area branch prediction using complementary branch predictors

Cited by 5 publications

References 19 publications

A survey of techniques for dynamic branch prediction

A survey of techniques for dynamic branch prediction

Cost-effective branch prediction by combining hedging and filtering

An Improved Dynamic Branch Predictor by Selective Access of a Specific Element in 4-Way Cache

Contact Info

Product

Resources

About