Low-power approximate MAC unit

Esposito, Darjn; Strollo, A.G.M.; Alioto, Massimo

doi:10.1109/prime.2017.7974112

Cited by 35 publications

(25 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Approximate 2/1 Compressor Let us consider the problem of summing two partial products belonging to the same column. As observed in [22], [25], and [28]:…”

Section: Proposed Approximate Compressorssupporting

confidence: 65%

“…It is worth noting that (6) was already used in [27] and [28]; it is also worth observing that the approximate 2 × 2 submultiplier of [10] can be obtained by using this approximate 2/1 compressor. In [25] an approximate half-adder is proposed, where an OR gate is used as sum output and an additional AND gate produces the carry output.…”

Section: Proposed Approximate Compressorsmentioning

confidence: 99%

“…In [27] a lossy compression of the partial-product rows, based on their bit significance, is proposed; this technique uses approximate half-adders (realized with simple OR gates) to generate a reduced set of product terms. A similar approach, using simple OR gates as approximate counters, is used in [28]. Architectural-space exploration of approximate arithmetic units is investigated in [29] where the authors propose four novels approximate multipliers, based on [10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Approximate Multipliers Based on New Approximate Compressors

Esposito

Strollo

Napoli

et al. 2018

IEEE Trans. Circuits Syst. I

Self Cite

191

View full text Add to dashboard Cite

Approximate computing is an emerging trend in digital design that trades off the requirement of exact computation for improved speed and power performance. This paper proposes novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers. By using the proposed approach, we have synthesized approximate multipliers for several operand lengths using a 40-nm library. Comparison with previously presented approximated multipliers shows that the proposed circuits provide better power or speed for a target precision. Applications to image filtering and to adaptive least mean squares filtering are also presented in the paper.

show abstract

“…Approximate 2/1 Compressor Let us consider the problem of summing two partial products belonging to the same column. As observed in [22], [25], and [28]:…”

Section: Proposed Approximate Compressorssupporting

confidence: 65%

Section: Proposed Approximate Compressorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Approximate Multipliers Based on New Approximate Compressors

Esposito

Strollo

Napoli

et al. 2018

IEEE Trans. Circuits Syst. I

Self Cite

191

View full text Add to dashboard Cite

show abstract

“…ate the inaccuracies of the approximate multiplier stage [35]. However, no exploitation of the self-healing methodology has been studied to the best of our knowledge.…”

Section: Background and Related Workmentioning

confidence: 99%

MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing

et al. 2019

View full text Add to dashboard Cite

Approximate computing studies the quality-efficiency trade-off to attain a best-efficiency (e.g., area, latency, and power) design for a given quality constraint and vice versa. Recently, self-healing methodologies for approximate computing have emerged that showed an effective quality-efficiency tradeoff as compared to the conventional error-restricted approximate computing methodologies. However, the state-of-the-art self-healing methodologies are constrained to highly parallel implementations with similar modules (or parts of a datapath) in multiples of two and for square-accumulate functions through the pairing of mirror versions to achieve error cancellation. In this paper, we propose a novel methodology for an internal-self-healing (ISH) that allows exploiting self-healing within a computing element internally without requiring a paired, parallel module, which extends the applicability to irregular/asymmetric datapaths while relieving the restriction of multiples of two for modules in a given datapath, as well as going beyond square functions. We employ our ISH methodology to design an approximate multiply-accumulate (xMAC), wherein the multiplier is regarded as an approximation stage and the accumulator as a healing stage. We propose to approximate a recursive multiplier in such a way that a near-to-zero average error is achieved for a given input distribution to cancel out the error at an accurate accumulation stage. To increase the efficacy of such a multiplier, we propose a novel 2 × 2 approximate multiplier design that alleviates the overflow problem within an n × n approximate recursive multiplier. The proposed ISH methodology shows a more effective quality-efficiency trade-off for an xMAC as compared with the conventional error-restricted methodologies for random inputs and for radio-astronomy calibration processing (up to 55% better quality output for equivalent-efficiency designs).

show abstract

“…However, a significant energy gain mandates approximating 40 out of the 64 bits of the results, which degrades the output quality significantly. An approximate MAC unit based on partial products compression and elimination, was proposed in [13]. The height of the partial products is reduced by using the OR gate for compression [14], [15], and the selected columns of partial products are not formed [16], [17].…”

Section: Related Workmentioning

confidence: 99%

Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency

2019

View full text Add to dashboard Cite

The Multiply-Accumulate Unit (MAC) is an integral computational component of all digital signal processing (DSP) architectures and thus has a significant impact on their speed and power dissipation. Due to an extraordinary explosion in the number of battery-powered ''Internet of Things'' (IoT) devices, the need for reducing the power consumption of DSP architectures has tremendously increased. Approximate computing (AxC) has been proposed as a potential solution for this problem targeting error-resilient applications. In this paper, we present a novel FPGA implementation for input-aware energy-efficient 8-bit approximate MAC (AxMAC) unit that reduces its power consumption by: performing multiplication operation approximately, or approximating the input operands then replacing multiplication by a simple shift operation. We propose an input-aware conditional block to bypass operands multiplication by (1) zero forwarding for zero-value operands, (2) judiciously approximating 43.8% of inputs into power-of-2 values, and (3) replacing the multiplication of power-of-2 operands by a simple shift operation. Experimental results show that these simplification techniques reduce delay, power and energy consumption with an acceptable quality degradation. We evaluate the effectiveness of the proposed AxMAC units on two image processing applications, i.e., image blending and filtering, and a logistic regression classification application. These applications demonstrate a negligible quality loss, with 66.6% energy reduction and 5% area overhead. INDEX TERMS Approximate computing, approximate multiplier, approximate multiple-accumulate unit (AxMAC), input-aware approximation, image processing, FPGA.

show abstract

Low-power approximate MAC unit

Cited by 35 publications

References 12 publications

Approximate Multipliers Based on New Approximate Compressors

Approximate Multipliers Based on New Approximate Compressors

MACISH: Designing Approximate MAC Accelerators With Internal-Self-Healing

Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency

Contact Info

Product

Resources

About