Low power and roboust FinFET SRAM cell using independent gate control

Bagheriye, Leila; Saeidi, Roghayeh; Toofan, Siroos

doi:10.1109/iscas.2016.7527167

Cited by 1 publication

(1 citation statement)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This provides a motivation to use Loihi as a hardware implementation platform for Bayesian inference. The FinFET technology used in the Loihi architecture is a promising technology in terms of energy and speed over conventional CMOS technology ( Bagheriye et al, 2016 ), while the use of emerging nonvolatile technologies attracts a lot of attention to developing ultra-low energy computing platforms for SNN-based Bayesian inference systems (like crossbar arrays discussed in Section “Crossbar Arrays for Bayesian Networks Implementation” ). However, the fabrication of robust nonvolatile devices and large-scale crossbar arrays probably require a lot more insights before they can outperform already highly developed technology and this approach is worth exploring.…”

Section: Hardware Implementation Of Probabilistic Spiking Neural Networkmentioning

confidence: 99%

Brain-Inspired Hardware Solutions for Inference in Bayesian Networks

Bagheriye

Kwisthout

2021

Front. Neurosci.

Self Cite

View full text Add to dashboard Cite

The implementation of inference (i.e., computing posterior probabilities) in Bayesian networks using a conventional computing paradigm turns out to be inefficient in terms of energy, time, and space, due to the substantial resources required by floating-point operations. A departure from conventional computing systems to make use of the high parallelism of Bayesian inference has attracted recent attention, particularly in the hardware implementation of Bayesian networks. These efforts lead to several implementations ranging from digital circuits, mixed-signal circuits, to analog circuits by leveraging new emerging nonvolatile devices. Several stochastic computing architectures using Bayesian stochastic variables have been proposed, from FPGA-like architectures to brain-inspired architectures such as crossbar arrays. This comprehensive review paper discusses different hardware implementations of Bayesian networks considering different devices, circuits, and architectures, as well as a more futuristic overview to solve existing hardware implementation problems.

show abstract

Section: Hardware Implementation Of Probabilistic Spiking Neural Networkmentioning

confidence: 99%