2008
DOI: 10.1049/iet-cdt:20050060
|View full text |Cite
|
Sign up to set email alerts
|

Low-power and error protection coding for network-on-chip traffic

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2010
2010
2017
2017

Publication Types

Select...
4
1

Relationship

0
5

Authors

Journals

citations
Cited by 7 publications
(1 citation statement)
references
References 1 publication
0
1
0
Order By: Relevance
“…According to [26, 27], an insufficient transfer rate and inefficient input/output access are the main causes of degraded performance in a system‐level design. Since the proposed SoC is an extension of the SMO learning core, the transfer rate must be increased to merge the three blocks, that is, the SMO learning core, butterfly‐path accelerator and SVM classification block.…”
Section: Proposed Tri‐layer Bus Soc With Butterfly‐path Acceleratormentioning
confidence: 99%
“…According to [26, 27], an insufficient transfer rate and inefficient input/output access are the main causes of degraded performance in a system‐level design. Since the proposed SoC is an extension of the SMO learning core, the transfer rate must be increased to merge the three blocks, that is, the SMO learning core, butterfly‐path accelerator and SVM classification block.…”
Section: Proposed Tri‐layer Bus Soc With Butterfly‐path Acceleratormentioning
confidence: 99%