Low power and area efficient semi-digital PLL for low bandwidth applications

Dietl, Markus; Sareen, Puneet

doi:10.1109/vdat.2011.5783546

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test 2011

DOI: 10.1109/vdat.2011.5783546

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Low power and area efficient semi-digital PLL for low bandwidth applications

Markus Dietl

Puneet Sareen

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Low power and area efficient semi-digital PLL for low bandwidth applications

Cited by 1 publication

References 5 publications

A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter

A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter

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