Low peak power ATPG for n-detection test

Fu, Kuo-Lin; Li, Katherine Shu-Min

doi:10.1109/iscas.2009.5118182

Cited by 9 publications

(2 citation statements)

References 13 publications

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“…The category contains various methods adopted to minimize the power consumption during external testing by ATE and depending on the number of transitions in test data set. [3] offer a heuristic method to produce a test sequences which create worst-case power droop by increasing the high-and low-frequency effects using a dynamically restrict to version of the classical D-algorithm for test generation. A novel scan chain division algorithm [4] analyzes the signal dependencies and creates the circuit partitions such that both shift and capture power can be reduced when using the existing ATPG flows.…”

Section: Iitesting Phenomena On Low Power Technologymentioning

confidence: 99%

Implementation of Low Power Circuit Analysis with Applications of Test Vectors

M¹,

S²,

M³

2015

International Journal of Innovative Research in Electrical, Ele

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An advanced approach to design a fault coverage test pattern generator by utilizing linear feedback shift register called Bit Swap-LFSR. This could perform fault analysis and also minimize the power utilization at circuit level during tests, by generating three intermediate patterns between random patterns by decreasing the hardware components usage. The main purpose of having intermediate patterns is to minimize the transitional processing at initial inputs; this could minimize the switching activities at circuit under test. By this the power consumption is decreased without any lose or damage in the hardware components. This experiment results by efficient multipliers circuits in proposed system, with and without fault confirm of fault coverage when the circuit has been tested.

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Section: Iitesting Phenomena On Low Power Technologymentioning

confidence: 99%

Implementation of Low Power Circuit Analysis with Applications of Test Vectors

M¹,

S²,

M³

2015

International Journal of Innovative Research in Electrical, Ele

View full text Add to dashboard Cite

show abstract

“…A novel scan chain division algorithm [7] analyzes the signal dependencies and creates the circuit partitions such that both shift and capture power can be reduced when using the existing ATPG flows. Reference [8] presents a low capture power ATPG and a power-aware test compaction method. This ATPG lowers the growth of test pattern count compared to the detection number n. The peak power becomes smaller as the detection number n increases.…”

Section: Low-power Atpg Algorithmsmentioning

confidence: 99%

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

2011

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Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.

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