Low-output-impedance BiCMOS voltage buffer

Bauwelinck, Johan; Chen, Wei; Verhulst, Dieter; Martens, Yves; Ossieur, Peter; Qiu, Xing-Zhi; Vandewege, Jan

doi:10.1587/elex.1.34

Cited by 4 publications

(3 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…signals (Sel and the inverted Sel) so that the voltage swing at the drain of the current source is reduced during switching [7]. We further improved the speed by using a unity-gain buffer to make the voltage at equal to the voltage at [8]. This makes a considerable difference because is fed into a current mirror of which the input voltage varies with the current.…”

Section: B Circuit Descriptionmentioning

confidence: 99%

A high-resolution burst-mode laser transmitter with fast and accurate level monitoring for 1.25 Gb/s upstream GPONs

Bauwelinck

Chen

Verhulst

et al. 2005

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-An innovative burst-mode laser transmitter (BM-TX)is presented for gigabit-capable passive optical network (GPON) upstream transmission at 1.25 Gb/s. The laser bias and modulation current each can reach 80 mA with a resolution of 0.1 mA providing a total drive current up to 160 mA. Both currents are generated by 10-bit current steering digital-to-analog converters (DACs), the architecture of which is specially adapted to yield a monotonic current setting at settling times below 12.8 ns. Tests show that fast automatic power control (APC) can stabilize and track the launched optical power with a tolerance of less than 1 dB over a wide temperature range for outdoor operation. The APC only requires a straightforward calibration of the "0" and the "1" level at room temperature. Optical level monitoring on strings of four consecutive "0" bytes and two consecutive "1" bytes at 1.25 Gb/s is demonstrated. APC based on such short strings of data has not been shown before.The circuits have been designed in a 0.35 m SiGe BiCMOS process. Experimental results show that this dc-coupled BM-TX meets the specifications of the recently approved ITU-T Recommendation G.984.2 supporting an intelligent power leveling mechanism (PLM).

show abstract

Section: B Circuit Descriptionmentioning

confidence: 99%

A high-resolution burst-mode laser transmitter with fast and accurate level monitoring for 1.25 Gb/s upstream GPONs

Bauwelinck

Chen

Verhulst

et al. 2005

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…The voltage buffer consists of a simple PMOS differential pair with unity-gain feedback. It sinks the current and serves the same purpose as the buffer in reference [14] although that buffer sources the current. The current is switched between 2 NMOS transistors, as controlled by the latch at the left-hand side of Fig.…”

Section: Latch Switch and Voltage Buffermentioning

confidence: 99%

A digitally controlled on-chip monotonic reference current generator with low LSB current for fast and accurate optical level monitoring

Chen

Bauwelinck

Ossieur

et al. 2007

Analog Integr Circ Sig Process

Self Cite

View full text Add to dashboard Cite

This paper describes a digitally controlled on-chip monotonic Reference Current Generator (RCG) with 8-bit resolution and a LSB (Least Significant Bit) current as low as 100 nA. It was designed as a building block of a generic DC-coupled Burst Mode Laser Diode Driver (BM-LDD) for GPON (Gigabit Passive Optical Network) applications and acts as an on-chip RCG with a settling time of 18 ns for fast and accurate optical level monitoring with guaranteed monotony. The proposed architecture of the on-chip RCG is based on an 8-bit segmented current-steering Digital-to-Analog Converter (IDAC) and a bandgap voltage reference. The (3 + 5) segmented architecture of the 8-bit IDAC is an optimum combination of a 3-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 5-bit LSBs binary-weighted sub-DAC offering good DNL (Differential Nonlinearity) performance. The bandgap voltage reference deviates only 0.6% of the nominal value over temperature and power supply variations. A cascade current mirror with a super beta helper circuit is used to guarantee monotony and high accuracy. The linearity errors caused by systematic influences and random variations are reduced by the proposed 2-D double centroid symmetrical architecture. Experiments confirm a DNL of +/- 0.5 LSB for the proposed RCG. The tested performance of optical level monitoring and APC (Automatic Power Control) algorithm is compliant to ITU-T GPON standards. The design was realized in a 0.35 mu m SiGe BiCMOS technology with 3.3 V power supply. The technology choice was made by heavy requirements of the innovative DC-coupled 1.25 Gbit/s BM-LDD chip. Although the proposed structure was designed as a building block for a BM-LDD chip, the design concept can be applied for developing other high linearity on-chip RCG for a wide junction temperature range (-40 to 110 degrees C)

show abstract

“…To minimize the settling time of the IDAC, a well-designed latch and two-way switch with a voltage buffer [11] is used. This low-power, 3.3 V BiCMOS voltage buffer is showing gigahertz operation, low output impedance and low input current.…”

Section: Latch Two-way Switch and Voltage Buffermentioning

confidence: 99%

A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers

Chen¹,

Bauwelinck²,

Ossieur³

et al. 2007

IEICE Transactions on Electronics

View full text Add to dashboard Cite

SUMMARYThis paper describes a current-steering Digital-to-Analog Converter (IDAC) architecture with a novel switching scheme, designed for GPON Burst Mode Laser Drivers (BMLD) and realized in a 0.35 µm SiGe BiCMOS technology with 3.3 V power supply. The (4+6) segmented architecture of the proposed 10-bit IDAC is optimized for minimum DNL (Differential Nonlinearity). It combines a 4-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 6-bit LSBs (Least Significant Bits) binaryweighted sub-DAC. A switching scheme based on this dedicated architecture yields a high monotony and a fast settling time. The linearity errors caused by systematic influences and random variations are reduced by the 2-D double centroid symmetrical architecture. Experimental results show that the DNL is below ± 0.5 LSB and that the settling time after the output current mirror is below 12 ns. Although the proposed IDAC architecture was designed for a BMLD chip, the design concept is generic and can be applied for developing other monotonic high-speed current-mode DACs. key words: current steering digital-to-analog converter, DNL, GPON, cascade current mirror, BiCMOS

show abstract

Low-output-impedance BiCMOS voltage buffer

Cited by 4 publications

References 2 publications

A high-resolution burst-mode laser transmitter with fast and accurate level monitoring for 1.25 Gb/s upstream GPONs

A high-resolution burst-mode laser transmitter with fast and accurate level monitoring for 1.25 Gb/s upstream GPONs

A digitally controlled on-chip monotonic reference current generator with low LSB current for fast and accurate optical level monitoring

A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers

Contact Info

Product

Resources

About