2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) 2014
DOI: 10.1109/iccdcs.2014.7016156
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Low noise Si based monolithic transimpedance amplifiers for 10 Gbps, 40 Gbps and 100 Gbps applications

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Cited by 4 publications
(6 citation statements)
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“…The proposed topology is a double cascode TIA with negative shunt-shunt feedback and inductive peaking techniques, optimized for very low noise performance [14][15][16][17]. Fig.…”
Section: The Proposed Circuit and Design Methodologymentioning
confidence: 99%
“…The proposed topology is a double cascode TIA with negative shunt-shunt feedback and inductive peaking techniques, optimized for very low noise performance [14][15][16][17]. Fig.…”
Section: The Proposed Circuit and Design Methodologymentioning
confidence: 99%
“…For these reasons we preferred to make use of a lumped element Darlington [23,24] circuit topology. This topology permits the achievement of a higher current gain cutoff frequency f t than each individual transistor, since it basically makes use of a proper HBT f t doubler technique [11,25]. Darlington topology is very compact and allows the design of very small size and low power consumption circuits, with an acceptable low noise performance [26].…”
Section: Inductor Less Darlington Ultra Wide Band Mm-wave Feedback Ammentioning
confidence: 99%
“…For transimpedance amplifiers [11,19,20], the optimization must be made as a function of the equivalent input noise current density, given in , and the transimpedance gain, derived from Sparameters:…”
Section: Inductor Less Darlington Ultra Wide Band Mm-wave Feedback Ammentioning
confidence: 99%
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