Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm

Abstract

A low noise phase locked loop (PLL) frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator (LO) carriers. Tested 11.5 GHz LO bears a phase noise of -104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm 2 , including bias circuits and buffers.

Low-noise sub-harmonic injection locked multiloop ring oscillator

“…However, it comes at the expense of noise performance degradation due to the additional PMOS FET for the second loop. References [3][4][5][6] show that the injection-locked technology can effectively decrease jitters in time-domain or phase noise in frequency-domain.…”