Low-noise and large-area CMOS SPADs with timing response free from slow tails

Abstract

This paper reports the design and the characterization of Single-Photon Avalanche Diodes (SPADs) fabricated in a standard 0.35 um CMOS technology aimed at very low noise and sharp timing response. We present the investigation on the breakdown voltage, photon detection efficiency (PDE), dark count rate (DCR) and timing response on devices with different dimensions and shapes of the active area. Results show uniform breakdown voltage among different structures, PDE above 50% at 420 nm, DCR below 50 cps at room temperature and timing response with no exponential tail and typical full-width at half-maximum of 77 ps and 120 ps for 10 um and 30 um active areas, respectively. The fabricated devices enable the fabrication of imagers with CMOS SPAD arrays suitable for advanced applications demanding extremely low noise and picosecond timing accuracy

Front-End Electronics for Silicon Photomultipliers

“…These designs are usually afflicted by a relatively high dark noise, characterized in SPADs by the dark count rate (DCR), mainly due to band-to-band tunneling and trap-assisted tunneling that results from reduced annealing and drive-in diffusion steps [79]. Recently, designs have emerged utilizing lightly doped layers that have helped reduce tunneling noise [30], while, in other designs, the noise was also reduced to 0.05 Hz/μm 2 with the use of special enrichment implants [80].…”

“…Photon counts can only be stored on pixel when a counter and a memory are integrated in situ, with the consequence of increasing the pitch. Among various substrate-isolated devices, SPADs designed with p+/n-well junctions, as reported by Bronzi [80], Leitner [92], Niclass [79], and Gersbach [78], have resulted in narrower PDP profiles due to the formation of a shallower junction. An alternative to this approach is the use of a memory of minimum size, 1 bit, or an analog counter.…”

Backside illuminated wafer-to-wafer bonding single photon avalanche diode array

“…To allow a more compact design, each SPAD is surrounded by a deep trench which prevents crosstalk and punch through effects. A first BackSPAD fabrication recipe exploited the same processing already employed in a previous CMOS SPADs batch [5], so the general layouts for the active part of both SPADs are identical. Fig.…”

“…These devices have been called "low-voltage" LV-BackSPAD, referring to the expected breakdown voltage that should be similar to the one achieved in [5]. We conceived a variant for exploiting a fully depleted silicon film when the SPAD device is under working conditions (i.e.…”

Characterization of Single-Photon Avalanche Diode arrays in 150nm CMOS technology

“…Since then several SPAD structures have been reported in different CMOS technology nodes. For instance, large-area SPADs with very low noise were realized in a 0.35μm CMOS process [5]. Small-area SPADs can be fabricated in deep-submicron process to create dense highresolution arrays [6].…”