2018 IEEE International Symposium on Circuits and Systems (ISCAS) 2018
DOI: 10.1109/iscas.2018.8351173
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Low Noise and High Photodetection Probability SPAD in 180 nm Standard CMOS Technology

Abstract: A square shaped, low noise and high photoresponse single photon avalanche diode suitable for circuit integration, implemented in a standard CMOS 180 nm high voltage technology, is presented. In this work, a p+ to shallow nwell junction was engineered with a very smooth electric field profile guard ring to attain a photo detection probability peak higher than 50% with a median dark count rate lower than 2 Hz/µm 2 when operated at an excess bias of 4 V. The reported timing jitter full width at half maximum is be… Show more

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Cited by 11 publications
(7 citation statements)
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“…Figure 9 shows the cumulative plot of the DCR at 1.4 V of overvoltage at room temperature. Almost 70% of the pixels have a dark count rate lower than 8 kHz, which is in line with other works [61,62]. Figure 10 shows a typical dark count profile of the SPAD sensor array at normal operation conditions.…”
Section: Resultssupporting
confidence: 88%
“…Figure 9 shows the cumulative plot of the DCR at 1.4 V of overvoltage at room temperature. Almost 70% of the pixels have a dark count rate lower than 8 kHz, which is in line with other works [61,62]. Figure 10 shows a typical dark count profile of the SPAD sensor array at normal operation conditions.…”
Section: Resultssupporting
confidence: 88%
“…1, if the DNW was placed underneath the p-well to isolate the active region of the SPAD from the p-substrate, the n-well guard ring will touch the DNW, thus making the p-well anode of the SPAD inaccessible. Third, compared to breakdown voltages of the SPADs with a very low DCR (23.5 V in [10], 16.8 V in [30], 25.46 V in [31]), the three n + /p-well SPADs in this work have a relatively low breakdown voltage (∼12.1 V). This means that the doping concentrations of the n + layer and p-well in this 180 nm standard CMOS process are higher, thus leading to a thinner depletion region and a higher probability for tunneling noise, which is in agreement with the low activation energy values for three SPADs shown in Fig.…”
Section: Performance Summary and Comparisonmentioning
confidence: 95%
“…Several reasons could be responsible for the higher dark noise. First, the three SPADs in this work are implemented in a fully standard CMOS process and no special layers such as buried-N layer in [10], [11] and [17], or deep p-well layer [30] are available to isolate the active region of SPADs from the noisy bulk. Second, even though the DNW is available in this 180 nm process, it cannot be used in this n + /p-well SPAD design since the bottom of the n-well reaches the DNW in this process.…”
Section: Performance Summary and Comparisonmentioning
confidence: 99%
“…Higher excess bias voltages also increase DCR since a higher electric field across the SPAD junction not only increases the likelihood of avalanche by photon detection, but also by noise sources. The DCR for current SPADs fabricated in CMOS technology can be optimized down to tens of Hz at room temperature [60,61].…”
Section: Silicon Photomultipliers (Sipms)mentioning
confidence: 99%