Low latency T-EMS decoder for non-binary LDPC codes

Li, Erbao; García-Herrero, Francisco; Declercq, David; Gunnam, Kiran; Lacruz, Jesus O.; Valls, Javier

doi:10.1109/acssc.2013.6810404

Cited by 18 publications

(64 citation statements)

References 13 publications

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“…Analyzing the implementation results from [17], where a T-EMS based decoder is presented, we conclude that the parallel trellis-based processing in the CN is the best solution for high-rate codes over high-order Galois fields. This is the main reason to use it as starting point to develop the solutions presented in this manuscript.…”

Section: Algorithm 3: T-ems Algorithmmentioning

confidence: 94%

“…The process for building the output messages ∆R m,n (a) has been greatly simplified with respect to the approach presented in [17]. In [17] ∆R m,n (a) generation is performed by subtracting from the extra column ∆Q(a) the contribution of symbols in which deviations were taken. On the other hand, when more than one configuration corresponds to the same output message value, the minimum value is considered as explained in Section 2.2.…”

Section: Check Node Architecturementioning

confidence: 99%

“…T-EMS offers the possibility of the parallel processing of messages in the decoder, which allows the design of high-speed decoders with higher throughput compared to previous proposals from literature. The first implementation of this algorithm, also made by this author [17], achieved a throughput of 484Mbps in a 90nm CMOS process after synthesis results for the (837,726) NB-LDPC code over GF (32). This previous work allowed the identification of bottlenecks in both algorithm and hardware architecture of T-EMS, and set the bases of this thesis.…”

Section: Thesis Structurementioning

confidence: 99%

“…We compare the TMM to the QSPA [6], and the recently published Relaxed Min-Max (RMM) [34] and T-EMS algorithms [17]. On Fig.…”

Section: Frame Error Rate Performancementioning

confidence: 99%

“…First, each proposal is analyzed individually; secondly, the impact of each proposal in the objectives of the thesis is studied. Next, a comparison between the starting-point [17] and the final results achieved during this thesis is made. The improvement in throughput is about 120%, whereas the reduction in area (measured in terms of NAND gates) is about 53%.…”

Section: Thesis Structurementioning

confidence: 99%

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VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz¹,

Jesús²

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This thesis studies the design of low-complexity soft-decision Non-Binary LowDensity Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps).In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended MinSum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput.Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm 2 . The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million iii NAND gates) is increased in almost five times compared to other proposals from literature.The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF (64) ResumenEn esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps).En la primera parte de la tesis los principales aspectos concernientes a los códi-gos NB-LDPC s...

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Section: Algorithm 3: T-ems Algorithmmentioning

confidence: 94%

Section: Check Node Architecturementioning

confidence: 99%