Low-Latency High-Throughput Systolic Multipliers Over &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$GF(2^{m})$&lt;/tex&gt; &lt;/formula&gt; for NIST Recommended Pentanomials

Xie, Jiafeng; Meher, Pramod Kumar; Mao, Zhi-Hong

doi:10.1109/tcsi.2014.2386782

Cited by 19 publications

(30 citation statements)

References 18 publications

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“…To be fair, we use the non-pipelined versions in comparisons due to the fact that other multiplications are non-pipelined designs. Table 5 lists the comparison of our design with the recent proposals of multiplications in [9,20,22,34], which clearly demonstrates that our design is more efficient than other multiplications, e.g. the time-area product is reduced by 76% in GF ((2 61 ) 2 ) and the time-area product is reduced by 87% in GF ((2 127 ) 2 ).…”

Section: 3mentioning

confidence: 81%

“…Table 5. Comparison of Our Design with Other multiplications in GF ((2 n ) 2 ) Pan et al [22] Xie et al [34] Namin et al [20] Hariri et al [9] Ours…”

Section: 3mentioning

confidence: 99%

“…We back up the claims with implementations of our design on TSMC-0.18µm standard cell CMOS ASIC and Altera, Xilinx FPGAs respectively. Experimental results and comparisons with other multiplications in [9,20,22,34] show that our design provides significant reductions in executing time and area.…”

mentioning

confidence: 93%

“…Finite field operations have gained increasing importance due to the fact that they are fundamental operations frequently encountered in areas of mathematic [1,5,23,26,27,29,[36][37][38] and engineering [4,7,16,28]. Generally, operations are computed via using a specific basis [2,3,6,9,10,13,[19][20][21][22]25,32,34,35], i.e. polynomial basis, normal basis, triangular basis, dual basis and other bases.…”

mentioning

confidence: 99%

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Efficient systolic multiplications in composite fields for cryptographic systems

Yi¹

2019

Discrete &Amp; Continuous Dynamical Systems - S

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Multiplications in finite fields are playing a key role in areas of cryptography and mathematic. We present approaches to exploit systolic architecture for multiplications in composite fields, which are expected to reduce the time-area product substantially. We design a pipelined architecture for multiplications in composite fields GF ((2 n) 2), where n is a positive integer. Besides, we design systolic architectures for multiplications and additions in finite fields GF (2 n). By integrating main improvements and other minor optimizations for multiplications in GF ((2 n) 2), the non-pipelined versions of our design takes 8n + 4 AND gates and 8n XOR gates to compute multiplications with the executing time of nT AN D + 4nT XOR , where T AN D and T XOR are delays of AND and XOR gates respectively; with the aid of pipelining, the pipelined version of our design has a throughput rate of one result per 2nT XOR. Other words, the time complexity and area complexity of our design are O(n). Thus, the complexity of time-area product of our design is O(n 2). Experimental results and comparisons show that our design provides significant reductions in executing time and area of multiplications. 2010 Mathematics Subject Classification. 12Y05.

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Section: 3mentioning

confidence: 81%

“…Table 5. Comparison of Our Design with Other multiplications in GF ((2 n ) 2 ) Pan et al [22] Xie et al [34] Namin et al [20] Hariri et al [9] Ours…”

Section: 3mentioning

confidence: 99%

mentioning

confidence: 93%

mentioning

confidence: 99%

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Efficient systolic multiplications in composite fields for cryptographic systems

Yi¹

2019

Discrete &Amp; Continuous Dynamical Systems - S

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“…Besides that, one has to note that the National Institute of Standards and Technology (NIST) has recommended five irreducible polynomials for ECC implementation [10,11] (three pentanomials and two trinomials). Without loss of generality, we can assume m 1 is a pentanomial and m 2 is a trinomial.…”

Section: Algorithm 1 Proposed Multiplication Algorithm For Hybrid Fimentioning

confidence: 99%

Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m)

Xie

2018

Symmetry

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Because of the efficient tradeoff in area-time complexities, digit-serial systolic multiplier over GF(2 m ) has gained substantial attention in the research community for possible application in current/emerging cryptosystems. In general, this type of multiplier is designed to be applicable to one certain field-size, which in fact determines the actual security level of the cryptosystem and thus limits the flexibility of the operation of cryptographic applications. Based on this consideration, in this paper, we propose a novel hybrid-size digit-serial systolic multiplier which not only offers flexibility to operate in either pentanomial-or trinomial-based multiplications, but also has low-complexity implementation performance. Overall, we have made two interdependent efforts to carry out the proposed work. First, a novel algorithm is derived to formulate the mathematical idea of the hybrid-size realization. Then, a novel digit-serial structure is obtained after efficient mapping from the proposed algorithm. Finally, the complexity analysis and comparison are given to demonstrate the efficiency of the proposed multiplier, e.g., the proposed one has less area-delay product (ADP) than the best existing trinomial-based design. The proposed multiplier can be used as a standard intellectual property (IP) core in many cryptographic applications for flexible operation.

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Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices

Ibrahim

Gebali²

2022

Alexandria Engineering Journal

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Low-Latency High-Throughput Systolic Multipliers Over <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> for NIST Recommended Pentanomials

Cited by 19 publications

References 18 publications

Efficient systolic multiplications in composite fields for cryptographic systems

Efficient systolic multiplications in composite fields for cryptographic systems

Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m)

Compact hardware accelerator for field multipliers suitable for use in ultra-low power IoT edge devices

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