Low-latency explicit communication and synchronization in scalable multi-core clusters

Abstract

Abstract-One of the main challenges in the multi-core area is the communication and synchronization of the cores and the design of an efficient interconnection network that is scalable to multiple cores. In this paper we present an efficient implementation of a scalable system that is targeting multicore systems. Each cluster node consists of 4 processors that support both explicit and implicit communication. Processor's cache is augmented with scratchpad and is merged with the network interface (NI) for reduced communication latency. All nodes are connected through a novel layer-2 switch that can support up to 20 nodes. The proposed system is designed and implemented using multiple FPGA boards and the performance evaluation presents the aggregate throughput of the system (with 16 processors) and the communication latency between that cluster nodes.

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

“…In order to make fast matching decision between the Input and Output Queues, several iterative matching algorithms have been proposed for CIOQ switches, such as PIM [23], iSLIP [25] and Dual Round Robin arbitration scheme (DRR) [24]. In this system we designed a more efficient matching algorithm combining the efficiency of PIM2 and the performance of DRR, called special Sequential Iterative Matching (SIM) [22]. In each iteration of the PIM matching algorithm two steps are performed; request and grant.…”

“…Six of these boards are interconnected through a Virtex2 board that serves as the central switch [22]. The measurement of the execution time has been performed in real-time on the FPGAs using hardware counter augmented to the Microblaze processors.…”