Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm

Zhu, Baozhou; Lei, Yuanwu; Peng, Yuanxi; He, Tingting

doi:10.1109/tcsi.2016.2631588

Cited by 16 publications

(7 citation statements)

References 32 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Very far less types of CORDIC gadgets than the prototypes [12] and [13] have been included in the proposed table. For CORDIC [14], [15] several architectural designs have been advanced. One of them is described in [17] and has a low latency, as opposed to the only one in [16].In keeping with this in mind, for revolution mode, after the CORDIC new release i = n/2, the place n is the complete huge form of bits inside the resultant vector, the x and y organizes (Xn/2+1 and Yn/2+1) are turned around with the aid of the final attitude, Wn/2+1, as follows:…”

Section: Fig31 Represent Ithnumber Repetition Fig32 Relationship Between I and Bitsmentioning

confidence: 99%

Scale Factor and Latency Analysis in CORDIC Processing Unit

Sharma¹

2021

TURCOMAT

View full text Add to dashboard Cite

Virtual laptop, cordic or synchronized, is a fast, quick, environmentally friendly algorithm for many applications used for the processing of digital signs. It typically uses an exquisite computing technique for the fixation of the trigonometrically relationships worried aboutrotation around plane coordinates and rectangular to polar shapeconversion, developed for actual airborne calculations. It contains a one-of-a-kind serial mathematics unit having 3 shift registers, 3 adders/sub tractors, appearance-up table and remarkable interconnections.

show abstract

Section: Fig31 Represent Ithnumber Repetition Fig32 Relationship Between I and Bitsmentioning

confidence: 99%

Scale Factor and Latency Analysis in CORDIC Processing Unit

Sharma¹

2021

TURCOMAT

View full text Add to dashboard Cite

show abstract

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

“…There are other CORDIC designs for computation of specific functions in FP format, such as [23], [33] and [27]. In [23] and [33], an architecture to compute only sine and cosine in FP format is proposed. To optimize the design, in the former the angle is introduced in fixed-point format whereas in the latter CORDIC is combined with Taylor expansion and rectangular multipliers.…”

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

Efficient Floating-Point Givens Rotation Unit

Hormigo,

Muñoz

2020

Preprint

View full text Add to dashboard Cite

High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, there are scarce works in hardware implementations of floating-point QR decomposition for embedded systems. In this paper, we propose a very efficient high-throughput floating-point Givens rotation unit for QR decomposition. Moreover, the initial proposed design for conventional number formats is enhanced by using the new Half-Unit Biased format. The provided error analysis shows the effectiveness of our proposals and the trade-off of different implementation parameters. FPGA implementation results are also presented and a thorough comparison between both approaches. These implementation results also reveal outstanding improvements compared to other previous similar designs in terms of area, latency, and throughput.

show abstract

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

“…There are other CORDIC designs for computation of specific functions in FP format, such as [5], [33] and [27]. In [5] and [33], an architecture to compute only sine and cosine in FP format is proposed. To optimize the design, in the former the angle is introduced in fixed-point format whereas in the latter CORDIC is combined with Taylor expansion and rectangular multipliers.…”

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

Efficient Floating-Point Givens Rotation Unit

Hormigo

Muñoz

2020

Circuits Syst Signal Process

View full text Add to dashboard Cite

High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, there are scarce works in hardware implementations of floating-point QR decomposition for embedded systems. In this paper, we propose a very efficient high-throughput floating-point Givens rotation unit for QR decomposition. Moreover, the initial proposed design for conventional number formats is enhanced by using the new Half-Unit Biased format. The provided error analysis shows the effectiveness of our proposals and the trade-off of different implementation parameters. We also present FPGA implementation results and a thorough comparison between both approaches. These implementation results also reveal outstanding improvements compared to other previous similar designs in terms of area, latency, and throughput.

show abstract

Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm

Cited by 16 publications

References 32 publications

Scale Factor and Latency Analysis in CORDIC Processing Unit

Scale Factor and Latency Analysis in CORDIC Processing Unit

Efficient Floating-Point Givens Rotation Unit

Efficient Floating-Point Givens Rotation Unit

Contact Info

Product

Resources

About