Low-frequency Noise in SiGe Channel pMOSFETs on Ultra-Thin Body SOI with Ni-Silicided Source/Drain

Haartman, Martin von; Hållstedt, Julius; Seger, Johan; Malm, B. Gunnar; Hellström, Per‐Erik; Östling, Mikael

doi:10.1063/1.2036756

Cited by 6 publications

(11 citation statements)

References 5 publications

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“…Note [93,4,86] that this self-heating effect only appears when power is being dissipated within the device (that is, when the transistor is on, conducting current through its channel). This [87,94]only occurs in CMOS circuits when a logic stage is switching state, not when it is in a stand-by state (e.g., holding a logic high or low state).…”

Section: Soi Challenges and Issuesmentioning

confidence: 99%

Silicon on Insulator Technology Review

Singh¹,

Saxena²,

Rastogi³

2011

IJESET

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Section: Soi Challenges and Issuesmentioning

confidence: 99%

Silicon on Insulator Technology Review

Singh¹,

Saxena²,

Rastogi³

2011

IJESET

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“…The simulation results show the field is relaxed along with fin width narrowing. Some papers reported flicker noise of MOS-FET on UTB FD SOI devices with fully depletion mode and larger flicker noise reduction was observed [16]. We think the lower flicker noise with below 50 nm fin width is caused by the lower the electrical field.…”

Section: Analog Performancementioning

confidence: 99%

Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

Ohguro

Inaba

Kaneko

et al. 2015

IEICE Trans. Electron.

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SUMMARY In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H 2 annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f T and f max , it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f T of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.

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“…It is now well accepted that the LF 1/f noise in FDSOI and multigate devices mostly stems from the fluctuations of the inversion charge nearby the two interfaces [3][4][5][6][7][8][9][10][11]. For UTBB devices, the gate oxide thickness reaches dimensions as small as nanometers, leading to larger surface roughness scattering playing an important role on carrier mobility and drain current fluctuations [12].…”

Section: Introductionmentioning

confidence: 99%

Semianalytical Modelling and 2D Numerical Simulation of Low-Frequency Noise in Advanced N-Channel FDSOI MOSFETs

Boutchacha

Ghibaudo

2020

Active and Passive Electronic Components

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Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.

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Low-frequency Noise in SiGe Channel pMOSFETs on Ultra-Thin Body SOI with Ni-Silicided Source/Drain

Cited by 6 publications

References 5 publications

Silicon on Insulator Technology Review

Silicon on Insulator Technology Review

Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

Semianalytical Modelling and 2D Numerical Simulation of Low-Frequency Noise in Advanced N-Channel FDSOI MOSFETs

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