Low Fixed Pattern Noise Current-mode Imager Using Velocity Saturated Readout Transistors

Abstract

This paper described a novel current-mode active pixel sensor (APS) imager. Conversion of photodiode voltage to output current is done using transistors operating in velocity saturation region. The high output impedance of this region makes it more suitable for current-sourcing operation than the linear region. The transistors also exhibit high linearity, allowing us to suppress fixed pattern noise (FPN) by correcting for both offset and gain variations among pixels. Experimental results on the fabricated 110×200 pixel array are presented. With conventional correlated double sampling (CDS), FPN is reduced from 3.8% to 0.85%. Further reduction requires compensation of gain variations, and results in a final FPN of 0.19%. A triple sampling approach is introduced to implement the described correction in hardware.

Current-mode image sensor with 1.5 transistors per pixel and improved dynamic range

“…Ideally, V re f and V pre have the same value. A large value is chosen, so that the readout transistor (M5) can be biased in velocity saturation [6]. The ADC is designed to operate at 10ns/bit and generate 11-bit digital output (10-bit effective after digital calibration).…”

“…3 shows a detailed timing diagram for reading out all PD1's in a column of pixel groups. It is assumed that FPN correction is done offline in order to achieve maximum frame rate; although on-chip hardware TS can also be implemented [6]. Under this assumption, only the signal levels at the end of integration needs to be read out.…”

“…5 as an example of FD voltage swing that yields good readout linearity. Since linearity deter- mines the effectiveness of TS [6], for a specific application, the exact amount of voltage swing should be set according to the FPN requirement. The swing is controlled by utilizing only a portion of the photodiode's full-well capacity.…”

“…Historically, voltage-mode APS were better than current-mode APS in spatial noise performance, because current output is more sensitive to gain variation (transistor W/L mismatch) among pixels [5]. However, we have demonstrated that one can suppress gain variation through a triple sampling (TS) approach, and obtain very low fixed pattern noise (FPN) [6]. This approach is feasible as long as current readout is linear, which is achieved in this design by biasing the readout transistor in velocity saturation.…”

High linearity current mode image sensor

“…However, of the readout transistor is still not constant, and the mismatch between the column switches reduces the precision. Others [2,6] proposed improving the linearity by biasing the readout transistor in velocity saturation region. Thus, a very short channel device and a higher drain to source voltage are required, which are limited by the CMOS processing technology.…”