Low-energy embedded FPGA structures

Kusse,; Rabaey,

doi:10.1109/lpe.1998.708181

Cited by 28 publications

(37 citation statements)

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“…In [41], power-gating is applied to the switches in the routing resources to reduce static power; duplicate routing resources, that use either high or low Vdd, are used to reduce dynamic power. In [30], energy-efficient modules for embedded components in FPGAs are introduced to reduce power by optimizing the number of connections between the module and the routing resources, and by using reduced supply voltage circuit techniques. In [27], several power reduction techniques, such as register file elimination and efficient instruction fetch, are proposed for a coarse-grain reconfigurable cell-based architecture; up to 3.6 times lower energy than an ARM7 device, and up to 6 times lower energy than a C55X DSP, is reported.…”

Section: Circuit-and Architecture-level Designmentioning

confidence: 99%

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Lamoureux

Luk

2008

2008 NASA/ESA Conference on Adaptive Hardware and Systems

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Section: Circuit-and Architecture-level Designmentioning

confidence: 99%

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

Lamoureux

Luk

2008

2008 NASA/ESA Conference on Adaptive Hardware and Systems

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“…It is described in [10], that for a Xilinx XC4003A FPGA, 65% of the power is attributed to interconnect, 21% to clock power, 9% to I/O power and only 5% to the actual calculations (CLB) power. Although this is an older FPGA device, new devices still focus on providing high speed switching matrices.…”

Section: Tdma -Time Division Multiple Accessmentioning

confidence: 99%

The happy marriage of architecture and application in next-generation reconfigurable systems

Verbauwhede

Schaumont

2004

Proceedings of the 1st Conference on Computing Frontiers

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New applications and standards are first conceived only for functional correctness and without concerns for the target architecture. The next challenge is to map them onto an architecture. Embedding such applications in a portable, low-energy context is the art of molding it onto an energyefficient target architecture combined with an energy efficient execution. With a reconfigurable architecture, this task becomes a two-way process where the architecture adapts to the application and vice-versa. This leads to the idea of a marriage between architecture and application.These next generation reconfigurable systems consist of a heterogeneous collection of domain-specific processing units. Communication between processors occurs over a reconfigurable interconnect scheme. Global control is provided by one or more embedded micro-controllers, which operate at a low frequency since they don't run compute intensive functions. Because of the domain specific features, this architecture is low power, yet at the same time reconfigurable.In this paper, we will describe the RINGS (Reconfigurable interconnect for next generation systems) architecture and the associated design environment, GEZEL. We will describe how applications are mapped onto RINGS architectures and how they can be modeled and simulated in the GEZEL environment.

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“…It provides low NRE (non-recurring engineering) cost and short time to market. Due to the large number of transistors required for field programmability and the low utilization rate of FPGA resources (typically 62.5% [1]), existing FPGAs consume more power compared to ASICs [2]. As the process advances to nanometer technologies and low-energy embedded applications are explored for FPGAs, power consumption becomes a crucial design constraint for FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Device and Architecture Cooptimization for FPGA Power Reduction

Cheng

Lin

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Device optimization considering supply voltage Vdd and threshold voltage Vt has little chip area increase, but a great impact on power and performance in the nanometer technology. This paper studies simultaneous evaluation of device and architecture optimization for FPGAs. We first develop an efficient yet accurate timing and power evaluation method, called trace-based model. By collecting trace information from cycleaccurate simulation of placed and routed FPGA benchmark circuits and re-using the trace for different Vdd and Vt, we enable device and architecture co-optimization considering hundreds of device and architecture combinations. Compared to the baseline FPGA architecture, which uses the VPR architecture model and the same LUT and cluster sizes as those used by the Xilinx Virtex-II, Vdd suggested by ITRS, and Vt optimized with respect to the above architecture and Vdd, architecture and device cooptimization can reduce energy-delay product by 20.5% and chip area by 23.3%. Furthermore, considering power-gating of unused logic blocks and interconnect switches (in this case sleep transistor size is a parameter of device tuning), our cooptimization reduces energy-delay product by 55.0% and chip area by 8.2% compared to the baseline FPGA architecture. To the best of our knowledge, this is the first in-depth study in the literature on architecture and device co-optimization for FPGAs.

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Low-energy embedded FPGA structures

Cited by 28 publications

References 0 publications

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays

The happy marriage of architecture and application in next-generation reconfigurable systems

Device and Architecture Cooptimization for FPGA Power Reduction

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